HCS12 datasheet(278/452 Pages) FREESCALE

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Instruction Glossary

S12CPUV2 Reference Manual, Rev. 4.0

278

Freescale Semiconductor

Operation:

If r1 bit 7 = 0, then $00 : (r1)

⇒ r2

If r1 bit 7 = 1, then $FF : (r1)

⇒ r2

Description:

This instruction is an alternate mnemonic for the TFR r1,r2 instruction,

where r1 is an 8-bit register and r2 is a 16-bit register. The result in r2 is the

16-bit sign extended representation of the original two’s complement

number in r1. The content of r1 is unchanged in all cases except that of SEX

A,D (D is A : B).

SEX

Sign Extend into 16-Bit Register

SEX

CCR Details:

HIN

––––––––

Source Form

Address

Mode

Object Code(1)

1. Legal coding for eb is summarized in the following table. Columns represent the high-order source digit. Rows represent

the low-order destination digit (MSB is a don’t care). Values are in hexadecimal.

Access Detail

HCS12

M68HC12

SEX abc,dxys

INH

B7 eb

sex:A

⇒ TMP2

sex:B

⇒ TMP2

sex:CCR

⇒ TMP2

sex:A

⇒ D

SEX A,D

sex:B

⇒ D

SEX B,D

sex:CCR

⇒ D

SEX CCR,D

sex:A

⇒ X

SEX A,X

sex:B

⇒ X

SEX B,X

sex:CCR

⇒ X

SEX CCR,X

sex:A

⇒ Y

SEX A,Y

sex:B

⇒ Y

SEX B,Y

sex:CCR

⇒ Y

SEX CCR,Y

sex:A

⇒ SP

SEX A,SP

sex:B

⇒ SP

SEX B,SP

sex:CCR

⇒ SP

SEX CCR,SP

HCS12 Datasheet(PDF) 278 Page - Freescale Semiconductor, Inc

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