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HCS12 Datasheet(PDF) 311 Page - Freescale Semiconductor, Inc |
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HCS12 Datasheet(HTML) 311 Page - Freescale Semiconductor, Inc |
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311 / 452 page  S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor 311 7.1 Introduction Exceptions are events that require processing outside the normal flow of instruction execution. This section describes exceptions and the way each is handled. 7.2 Types of Exceptions Central processor unit (CPU12) exceptions include: • Resets – Power-on reset and RESET pin – Clock monitor reset – COP watchdog reset • An unimplemented opcode trap • A software interrupt instruction (SWI) • Non-maskable (X-bit) interrupts • Maskable (I-bit) interrupts Each exception has an associated 16-bit vector, which points to the memory location where the routine that handles the exception is located. As shown in Table 7-1, vectors are stored in the upper bytes of the standard 64-Kbyte address map. The six highest vector addresses are used for resets and unmaskable interrupt sources. The remaining vectors are used for maskable interrupts. All vectors must be programmed to point to the address of the appropriate service routine. Reference Manual — S12CPUV2 Section 7. Exception Processing |
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