HCS12 datasheet(315/452 Pages) FREESCALE

315 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

315

7.5 Interrupts

Each HCS12 device can recognize a number of interrupt sources. Each

source has a vector in the vector table. The XIRQ signal, the unimplemented

opcode trap, and the SWI instruction are non-maskable, and have a fixed

priority. The remaining interrupt sources can be masked by the I bit. In most

devices, the external interrupt request pin is assigned the highest maskable

interrupt priority, and the internal periodic real-time interrupt generator has

the next highest priority. Other maskable interrupts are associated with

on-chip peripherals such as timers or serial ports. These maskable sources

have default priorities that follow the address order of the interrupt vectors.

The higher the vector address, the higher the priority of the interrupt. On The

HCS12, a device integration module incorporates logic that can give any

one maskable source priority over other maskable sources.

7.5.1 Non-Maskable Interrupt Request (XIRQ)

The XIRQ input is an updated version of the non-maskable interrupt (NMI)

input of earlier MCUs. The XIRQ function is disabled during system reset

and upon entering the interrupt service routine for an XIRQ interrupt.

During reset, both the I bit and the X bit in the CCR are set. This disables

maskable interrupts and interrupt service requests made by asserting the

XIRQ signal. After minimum system initialization, software can clear the X

bit using an instruction such as ANDCC #$BF. Software cannot set the X bit

from 0 to 1 once it has been cleared, and interrupt requests made via the

XIRQ pin become non-maskable. When a non-maskable interrupt is

recognized, both the X and I bits are set after context is saved. The X bit is

not affected by maskable interrupts. Execution of an return-from-interrupt

(RTI) instruction at the end of the interrupt service routine normally restores

the X and I bits to the pre-interrupt request state.

7.5.2 Maskable Interrupts

Maskable interrupt sources include on-chip peripheral systems and external

interrupt service requests. Interrupts from these sources are recognized

when the global interrupt mask bit (I) in the CCR is cleared. The default state

of the I bit out of reset is 1, but it can be written at any time.

The interrupt module manages maskable interrupt priorities. Typically, an

on-chip interrupt source is subject to masking by associated bits in control

registers in addition to global masking by the I bit in the CCR. Sources

HCS12 Datasheet(PDF) 315 Page - Freescale Semiconductor, Inc