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HCS12 Datasheet(PDF) 123 Page - Freescale Semiconductor, Inc |
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HCS12 Datasheet(HTML) 123 Page - Freescale Semiconductor, Inc |
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123 / 452 page ![]() S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor 123 Description: BGND operates like a software interrupt, except that no registers are stacked. First, the current PC value is stored in internal CPU register TMP2. Next, the BDM ROM and background register block become active. The BDM ROM contains a substitute vector, mapped to the address of the software interrupt vector, which points to routines in the BDM ROM that control background operation. The substitute vector is fetched, and execution continues from the address that it points to. Finally, the CPU checks the location that TMP2 points to. If the value stored in that location is $00 (the BGND opcode), TMP2 is incremented, so that the instruction that follows the BGND instruction is the first instruction executed when normal program execution resumes. For all other types of BDM entry, the CPU performs the same sequence of operations as for a BGND instruction, but the value stored in TMP2 already points to the instruction that would have executed next had BDM not become active. If active BDM is triggered just as a BGND instruction is about to execute, the BDM firmware does increment TMP2, but the change does not affect resumption of normal execution. While BDM is active, the CPU executes debugging commands received via a special single-wire serial interface. BDM is terminated by the execution of specific debugging commands. Upon exit from BDM, the background/boot ROM and registers are disabled, the instruction queue is refilled starting with the return address pointed to by TMP2, and normal processing resumes. BDM is normally disabled to avoid accidental entry. While BDM is disabled, BGND executes as described, but the firmware causes execution to return to the user program. Refer to Section 8. Instruction Queue for more information concerning BDM. BGND Enter Background Debug Mode BGND CCR Details: S X HIN Z V C –––––––– Source Form Address Mode Object Code Access Detail HCS12 M68HC12 BGND INH 00 VfPPP VfPPP |
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