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HCS12 Datasheet(PDF) 124 Page - Freescale Semiconductor, Inc |
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HCS12 Datasheet(HTML) 124 Page - Freescale Semiconductor, Inc |
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124 / 452 page  S12CPUV2 Reference Manual, Rev. 4.0 124 Freescale Semiconductor Operation: If Z + (N ⊕ V) = 0, then (PC) + $0002 + Rel ⇒ PC For signed two’s complement values if (Accumulator) > (Memory), then branch Description: BGT can be used to branch after comparing or subtracting signed two’s complement values. After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value is greater than the value in M. After CBA or SBA, the branch occurs if the value in B is greater than the value in A. See 3.8 Relative Addressing Mode for details of branch execution. BGT Branch if Greater than Zero BGT CCR Details: S X HIN Z V C –––––––– Source Form Address Mode Object Code Access Detail HCS12 M68HC12 BGT rel8 REL 2E rr PPP/P(1) 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken. PPP/P(1) Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r>m BGT 2E Z + (N ⊕ V) = 0 r ≤m BLE 2F Signed r ≥m BGE 2C N ⊕ V = 0 r<m BLT 2D Signed r=m BEQ 27 Z = 1 r ≠m BNE 26 Signed r ≤m BLE 2F Z + (N ⊕ V) = 1 r>m BGT 2E Signed r<m BLT 2D N ⊕ V = 1 r ≥m BGE 2C Signed r>m BHI 22 C + Z = 0 r ≤m BLS 23 Unsigned r ≥m BHS/BCC 24 C = 0 r<m BLO/BCS 25 Unsigned r=m BEQ 27 Z = 1 r ≠m BNE 26 Unsigned r ≤m BLS 23 C + Z = 1 r>m BHI 22 Unsigned r<m BLO/BCS 25 C = 1 r ≥m BHS/BCC 24 Unsigned Carry BCS 25 C = 1 No Carry BCC 24 Simple Negative BMI 2B N = 1 Plus BPL 2A Simple Overflow BVS 29 V = 1 No Overflow BVC 28 Simple r=0 BEQ 27 Z = 1 r ≠0 BNE 26 Simple Always BRA 20 — Never BRN 21 Unconditional |
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