HCS12 datasheet(163/452 Pages) FREESCALE

163 / 452 page

Glossary

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

163

Operation:

(Counter) – 1

⇒ Counter

If (Counter) not = 0, then (PC) + $0003 + Rel

⇒ PC

Description:

Subtract one from the specified counter register A, B, D, X, Y, or SP. If the

counter register has not been decremented to zero, execute a branch to the

specified relative destination. The DBNE instruction is encoded into three

bytes of machine code including a 9-bit relative offset (–256 to

+255

locations from the start of the next instruction).

IBNE and TBNE instructions are similar to DBNE except that the counter is

incremented or tested rather than being decremented. Bits 7 and 6 of the

instruction postbyte are used to determine which operation is to be

performed.

DBNE Decrement and Branch if Not Equal to Zero DBNE

CCR Details:

HIN

––––––––

Source Form

Address

Mode

Object Code(1)

1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero (DBEQ – 0)

or not zero (DBNE – 1) versions, and bit 4 is the sign bit of the 9-bit relative offset. Bits 7 and 6 would be 0:0 for DBNE.

Access Detail

HCS12

M68HC12

DBNE abdxys, rel9

REL

04 lb rr

PPP/PPO

PPP

Count

Bits 2:0

Source Form

Object Code

(If Offset is Positive)

Object Code

(If Offset is Negative)

000

001

DBNE A, rel9

DBNE B, rel9

04 20 rr

04 21 rr

04 30 rr

04 31 rr

100

101

110

111

DBNE D, rel9

DBNE X, rel9

DBNE Y, rel9

DBNE SP, rel9

04 24 rr

04 25 rr

04 26 rr

04 27 rr

04 34 rr

04 35 rr

04 36 rr

04 37 rr

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