TAS5508C datasheet(6/107 Pages) TI

6 / 107 page

TAS5508C

SLES257 – SEPTEMBER 2010

www.ti.com

List of Figures

1-1

TAS5508C Functional Structure

................................................................................................ 12

1-2

Typical TAS5508C Application (DVD Receiver)

............................................................................. 12

1-3

Recommended TAS5508C and TAS5121 Channel Configuraton

......................................................... 13

2-1

TAS5508C DAP Architecture With I

2C Registers (Fs ≤ 96 kHz)

........................................................... 23

2-2

TAS5508C Architecture With I

2C Registers (Fs = 176.4 kHz or Fs = 192 kHz)

......................................... 24

2-3

TAS5508C Detailed Channel Processing

..................................................................................... 24

2-4

5.23 Format

....................................................................................................................... 25

2-5

Conversion Weighting Factors—5.23 Format to Floating Point

............................................................ 25

2-6

Alignment of 5.23 Coefficient in 32-Bit I

2C Word

............................................................................. 25

2-7

25.23 Format

...................................................................................................................... 26

2-8

Alignment of 5.23 Coefficient in 32-Bit I

2C Word

............................................................................. 26

2-9

Alignment of 25.23 Coefficient in Two 32-Bit I

2C Words

.................................................................... 27

2-10

TAS5508C Digital Audio Processing

.......................................................................................... 28

2-11

Input Crossbar Mixer

............................................................................................................. 28

2-12

Biquad Filter Structure

........................................................................................................... 29

2-13

Automute Threshold

............................................................................................................. 31

2-14

Loudness Compensation Functional Block Diagram

........................................................................ 32

2-15

Loudness Example Plots

........................................................................................................ 33

2-16

DRC Positioning in TAS5508C Processing Flow

............................................................................ 34

2-17

Dynamic Range Compression (DRC) Transfer Function Structure

........................................................ 35

2-18

Output Mixers

..................................................................................................................... 39

2-19

De-Emphasis Filter Characteristics

............................................................................................ 40

2-20

Power-Supply and Digital Gains (Log Space)

................................................................................ 41

2-21

Power-Supply and Digital Gains (Linear Space)

............................................................................. 41

2-22

Block Diagrams of Typical Systems Requiring TAS5508C Automatic AM Interference-Avoidance Circuit

.......... 42

4-1

Slave Mode Serial Data Interface Timing

..................................................................................... 57

4-2

SCL and SDA Timing

............................................................................................................ 58

4-3

Start and Stop Conditions Timing

.............................................................................................. 58

4-4

Reset Timing

...................................................................................................................... 59

4-5

Power-Down Timing

............................................................................................................. 59

4-6

Error Recovery Timing

........................................................................................................... 60

4-7

Mute Timing

....................................................................................................................... 60

4-8

HP_SEL Timing

................................................................................................................... 62

4-9

2S 64-Fs Format

................................................................................................................. 63

4-10

Left-Justified 64-Fs Format

..................................................................................................... 63

4-11

Right-Justified 64-Fs Format

.................................................................................................... 64

5-1

Typical I

2C Sequence

............................................................................................................ 65

5-2

Single-Byte Write Transfer

...................................................................................................... 66

5-3

Multiple-Byte Write Transfer

.................................................................................................... 67

5-4

Single-Byte Read Transfer

...................................................................................................... 68

5-5

Multiple-Byte Read Transfer

.................................................................................................... 68

List of Figures

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