TAS5508C datasheet(65/107 Pages) TI

65 / 107 page

7-BitSlave Address

8-BitRegister Address(N)

8-BitRegisterDataFor

Address(N)

Start

Stop

SDA

SCL

8-BitRegisterDataFor

Address(N)

T0035-01

TAS5508C

www.ti.com

SLES257 – SEPTEMBER 2010

2C Serial-Control Interface (Slave Address 0x36)

The TAS5508C has a bidirectional I2C interface that is compatible with the Inter-IC (I2C) bus protocol and

supports both 100-kbps and 400-kbps data transfer rates for single- and multiple-byte write and read

operations. This is a slave-only device that does not support a multimaster bus environment or wait state

insertion. The control interface is used to program the registers of the device and to read device status.

The TAS5508C supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus

operation (400 kHz maximum). The TAS5508C performs all I2C operations without I2C wait cycles.

5.1

General I

2C Operation

The I2C bus employs two signals—SDA (data) and SCL (clock)—to communicate between integrated

circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data can be

transferred in byte (8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte

transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer

operation begins with the master device driving a start condition on the bus and ends with the master

device driving a stop condition on the bus. The bus uses transitions on SDA while the clock is high to

indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high

transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period.

These conditions are shown in Figure 5-1. The master generates the 7-bit slave address and the

read/write (R/W) bit to open communication with another device and then wait for an acknowledge

condition. The TAS5508C holds SDA low during the acknowledge clock period to indicate an

acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is

addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same

signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for

the SDA and SCL signals to set the high level for the bus.

Figure 5-1. Typical I2C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When

the last word transfers, the master generates a stop condition to release the bus. A generic data transfer

sequence is shown in Figure 5-1.

The 7-bit address for the TAS5508C is 0011011.

5.2

Single- and Multiple-Byte Transfers

The serial-control interface supports both single-byte and multiple-byte read/write operations for status

registers and the general control registers associated with the PWM. However, for the DAP data

processing registers, the serial-control interface supports only multiple-byte (four-byte) read/write

operations.

During multiple-byte read operations, the TAS5508C responds with data, a byte at a time, starting at the

subaddress assigned, as long as the master device continues to respond with acknowledges. If a

particular subaddress does not contain 32 bits, the unused bits are read as logic 0.

I2C Serial-Control Interface (Slave Address 0x36)

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