R26 datasheet(214/487 Pages) RENESAS

214 / 487 page

R8C/26 Group, R8C/27 Group

14. Timers

Rev.2.10

Sep 26, 2008

Page 195 of 453

REJ09B0278-0210

Figure 14.39

Buffer Operation for Output Compare Function

Make the following settings in timer mode.

• To use the TRCGRC register as the buffer register for the TRCGRA register:

Set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.

• To use the TRCGRD register as the buffer register for the TRCGRB register:

Set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.

The output compare function, PWM mode, or PWM2 mode, and the TRCGRC or TRCGRD register is

functioning as a buffer register, the IMFC bit or IMFD bit in the TRCSR register is set to 1 when a compare

match with the TRC register occurs.

The input capture function and the TRCGRC register or TRCGRD register is functioning as a buffer register,

the IMFC bit or IMFD bit in the TRCSR register is set to 1 at the input edge of a signal input to the TRCIOC pin

or TRCIOD pin.

TRCGRA register

m-1

m+1

TRC register

The above applies under the following conditions:

• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).

• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 001b (“L” output at compare match).

Transfer

TRCGRC register

(buffer)

TRCIOA output

TRCGRC

TRCGRA

Comparator

TRC

Compare match signal

R26 Datasheet(PDF) 214 Page - Renesas Technology Corp