R26 datasheet(215/487 Pages) RENESAS

215 / 487 page

R8C/26 Group, R8C/27 Group

14. Timers

Rev.2.10

Sep 26, 2008

Page 196 of 453

REJ09B0278-0210

14.3.3.3

Digital Filter

The input to TRCTRG or TRCIOj (j = A, B, C, or D) is sampled, and the level is considered to be determined

when three matches occur. The digital filter function and sampling clock are selected using the TRCDF register.

Figure 14.40 shows a Block Diagram of Digital Filter.

Figure 14.40

Block Diagram of Digital Filter

Latch

Match detect

circuit

Edge detect

circuit

DFj (or DFTRG)

Sampling clock

IOA2 to IOA0

IOB2 to IOB0

IOC2 to IOC0

IOD2 to IOD0

(or TCEG1 to TCEG0)

DFCK1 to DFCK0

TRCIOj input signal

(or TRCTRG input

signal)

Clock cycle selected by

TCK2 to TCK0

(or DFCK1 to DFCK0)

Sampling clock

TRCIOj input signal

(or TRCTRG input signal)

Input signal after passing

through digital filter

If fewer than three matches occur,

the matches are treated as noise

and no transmission is performed.

Maximum signal transmission

delay is five sampling clock

pulses.

Three matches occur and a

signal change is confirmed.

f32

j = A, B, C, or D

TCK0 to TCK2: Bits in TRCCR1 register

DFTRG, DFCK0 to DFCK1, DFj: Bits in TRCDF register

IOA0 to IOA2, IOB0 to IOB2: Bits in TRCIOR0 register

IOC0 to IOC2, IOD0 to IOD2: Bits in TRCIOR1 register

TCEG1 to TCEG0: Bits in TRCCR2 register

Latch

Timer RC operation clock

f1 or fOCO40M

Count source

= 00b

= 01b

= 10b

= 11b

TCK2 to TCK0

= 001b

= 010b

= 011b

= 000b

= 100b

= 101b

f32

TRCCLK

fOCO40M

= 110b

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