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TLE5012

Specification

Target Data Sheet

V 0.46, 2009-09

3.4.6

Clock Supply (CLK Timing Definition)

If the external clock supply is selected, the clock signal input ’CLK’ must fulfill certain requirements which are

described in the following:

•

The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse

width and must be spike filtered.

•

The duty cycle factor should be 0.5 but can deviate to the values limited by tCLKh(f_min) and tCLKl(f_min).

•

The PLL is triggered at the positive edge of the clock. If more than 2 edges are missing, a chip reset is

generated automatically.

Figure 13

External CLK Timing Definition

Table 9

CLK Timing Specification

Parameter

Symbol

Values

Unit

Note / Test Condition

Min.

Typ.

Max.

Input Frequency

fCLK

3.8

4.0

4.2

MHz

CLK Duty Cycle1)2)

1) Minimum Duty Cycle Factor: tCLKh(f_min) / tCLK(f_min) with tCLK(f_min)= 1 / fCLK(f_min)

2) Maximum Duty Cycle Factor: tCLKh(f_max) / tCLK(f_min) with tCLKh(f_max)= tCLK(f_min) - tCLKl(min)

CLKDUTY

CLK Rise Time

tCLKr

from VL to VH

CLK Fall Time

tCLKf

from VH to VL

Digital Clock

fDIG

22.8

25.2

MHz

Internal Oscillator Frequency

fCLK

3.8

4.0

4.2

MHz

tCLKh

tCLKl

tCLK

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