ADRF6801 datasheet(4/36 Pages) AD

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ADRF6801

Rev. 0 | Page 4 of 36

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

PHASE NOISE (USING 130 kHz LOOP FILTER)

fLO = 900 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured

at BB outputs with fBB = 50 MHz

1 kHz offset

−99.5

dBc/Hz

10 kHz offset

−107.8

dBc/Hz

100 kHz offset

−106.6

dBc/Hz

500 kHz offset

−126.7

dBc/Hz

1 MHz offset

−131.7

dBc/Hz

5 MHz offset

−143.5

dBc/Hz

10 MHz offset

−150.5

dBc/Hz

Integrated Phase Noise

1 kHz to 10 MHz integration bandwidth

0.16

°rms

PHASE NOISE (USING 2.5 kHz LOOP FILTER)

fLO = 900 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured

at BB outputs with fBB = 50 MHz

1 kHz offset

−71.3

dBc/Hz

10 kHz offset

−88.3

dBc/Hz

100 kHz offset

−114.1

dBc/Hz

500 kHz offset

−129.5

dBc/Hz

1 MHz offset

−138.6

dBc/Hz

5 MHz offset

−150.2

dBc/Hz

10 MHz offset

−150.3

dBc/Hz

PLL FIGURE OF MERIT (FOM)

Measured with fREF = 26 MHz, fPFD = 26 MHz

−215.4

dBc/Hz/Hz

Measured with fREF = 104 MHz, fPFD = 26 MHz

−220.9

dBc/Hz/Hz

Phase Detector Frequency

MHz

REFERENCE CHARACTERISTICS

REFIN, MUXOUT pins

REFIN Input Frequency

Usable range

160

MHz

REFIN Input Capacitance

MUXOUT Output Level

VOL (lock detect output selected)

0.25

VOH (lock detect output selected)

2.7

REFOUT Duty Cycle

CHARGE PUMP

Pump Current

500

μA

Output Compliance Range

2.8

LOGIC INPUTS

CLK, DATA, LE pins

Input High Voltage, VINH

1.4

3.3

Input Low Voltage, VINL

0.7

Input Current, IINH/IINL

0.1

μA

Input Capacitance, CIN

POWER SUPPLIES

VCC1, VCC2, VCCLO, VCCBB, VCCRF pins

Voltage Range (5 V)

4.75

5.25

Supply Current (5 V)

Normal Rx mode, internal LO

262

Rx mode, internal LO with LO buffer enabled

288

Rx mode, using external LO input (internal VCO, PLL shut

down)

157

Supply Current (5 V)

Power-down mode

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