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ADRF6801 Datasheet(PDF) 7 Page - Analog Devices

Part # ADRF6801
Description  750 MHz to 1150 MHz Quadrature Demodulator with Fractional-N PLL and VCO
PDF  36 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADRF6801 Datasheet(HTML) 7 Page - Analog Devices

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ADRF6801
Rev. 0 | Page 7 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
THIRD-ORDER
SDM
VCO
BAND
CURRENT
CAL/SET
VCO
3000MHz
TO
4600MHz
PHASE DETECTOR
AND
CHARGE PUMP
QUADRATURE
÷2
SERIAL PORT
×
2
ENABLE
PROGRAMABLE
DIVIDER
÷4
MUX
PRESCALER
÷2
VCO
LDO
2.5V
LDO
MUX
INTEGER
FRACTION
6
6
BLEED
SCALE
MODULUS
BUFFER
CTRL
DIV
CTRL
÷2
DIV
÷1
OR
÷2
VCC1 1
DECL3 2
CPOUT 3
GND 4
RSET 5
REFIN 6
GND 7
MUXOUT 8
DECL2 9
VCC2 10
23 GND
24 GND
25 GNDRF
26 RFIN
27 VCCRF
28 GND
29 VCCBB
30 GND
22 VCCBB
21 GND
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VCC1
The 5 V Power Supply Pin for VCO and PLL (VCC1).
2
DECL3
Decoupling Node for the 3.3 V LDO. Connect a 0.1 μF capacitor between this pin and ground.
3
CPOUT
Charge Pump Output Pin. Connect this pin to VTUNE through the loop filter.
4, 7, 11, 15, 16, 20, 21,
23, 24, 28, 30, 31, 35
GND
Connect these pins to a low impedance ground plane.



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