ADRF6801 datasheet(14/36 Pages) AD

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ADRF6801

Rev. 0 | Page 14 of 36

CIRCUIT DESCRIPTION

The ADRF6801 integrates a high performance IQ demodulator

with a state-of-the-art fractional-N PLL. The PLL also integrates

a low noise VCO. The SPI port allows the user to control the

fractional-N PLL functions, the demodulator LO divider functions,

and optimization functions, as well as allowing for an externally

applied LO.

The ADRF6801 uses a high performance mixer core that results

in an exceptional input IP3 and input P1dB, with a very low output

noise floor for excellent dynamic range.

LO QUADRATURE DRIVE

A signal at 2× the desired mixer LO frequency is delivered to

a divide-by-2 quadrature phase splitter followed by limiting

amplifiers which then drive the I and Q mixers, respectively.

V-TO-I CONVERTER

The RF input signal is applied to an on-chip balun which then

provides both a ground referenced, 50 Ω single-ended input

impedance and a differential voltage output to a V-to-I converter

that converts the differential voltages to differential output currents.

These currents are then applied to the emitters of the Gilbert

cell mixers.

MIXERS

The ADRF6801 has two double-balanced mixers: one for the

in-phase channel (I channel) and one for the quadrature channel

(Q channel). These mixers are based on the Gilbert cell design

of four cross-connected transistors. The output currents from

the two mixers are summed together in the resistive loads that

then feed into the subsequent emitter follower buffers.

EMITTER FOLLOWER BUFFERS

The output emitter followers drive the differential I and Q signals

off chip. The output impedance is set by on-chip 12 Ω series

resistors that yield a 24 Ω differential output impedance for each

baseband port. The fixed output impedance forms a voltage divider

with the load impedance that reduces the effective gain. For example,

a 500 Ω differential load has ~0.5 dB lower effective gain than

with a high (10 kΩ) differential load impedance.

The common-mode dc output levels of the emitter followers are set

from VCCBB via the voltage drop across the mixer load resistors,

the VBE of the output emitter follower, and the voltage drop

across the 12 Ω series resistor.

BIAS CIRCUITRY

There are several band gap reference circuits and three low

dropout regulators (LDOs) in the ADRF6801 that generate the

reference currents and voltages used by different sections. The

first of the LDOs is the 2.5 V LDO, which is always active and

provides the 2.5 V supply rail used by the internal digital logic

blocks. The 2.5 V LDO output is connected to DECL2 (Pin 9)

for the user to provide external decoupling.

The second LDO is the VCO LDO, which acts as the positive

supply rail for the internal VCO. The VCO LDO output is

connected to DECL2 (Pin 40) for the user to provide external

decoupling. The VCO LDO can be powered down by setting

not using the VCO.

The third LDO is the 3.3 V LDO, which acts as the 3.3 V

positive supply rail for the reference input, phase frequency

detector, and charge pump circuitry. The 3.3 V LDO output is

connected to DECL3 (Pin 2) for the user to provide external

decoupling. The 3.3 V LDO can be powered down by setting

not using the VCO. The demodulator also has a bias circuit that

supplies bias current for the mixer V-to-I stage, which then sets

the bias for the mixer core. The demodulator bias cell can also

be shut down by setting Register 5, DB7 = 0.

The ADRF6801 provides access to its many programmable

features through a 3-wire SPI control interface that is used to

program the seven internal registers. The minimum delay and

hold times are shown in the timing diagram (see Figure 2). The

SPI provides digital control of the internal PLL/VCO as well as

several other features related to the demodulator core, on-chip

referencing, and available system monitoring functions. The

MUXOUT pin provides a convenient, single-pin monitor output

signal that can be used to deliver a PLL lock-detect signal or an

internal voltage proportional to the local junction temperature.

Note that internal calibration for the PLL must run when the

ADRF6801 is initialized at a given frequency. This calibration is run

automatically whenever Register 0, Register 1, or Register 2 is

programmed. Because the other registers affect PLL performance,

last. For ease of use, starting the initial programming with

order, ending with Register 0, is recommended. Once the PLL

and other settings are programmed, the user can change the

PLL frequency simply by programming Register 0, Register 1,

or Register 2 as necessary.

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