33810 datasheet(21/37 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33810

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Figure 7. Open Secondary Spark Event

The Open Secondary timer is initiated on the rising edge

of the ignition coil primary spark signal and terminated on the

falling edge. The rising edge Open Secondary Threshold is

VIH= 135 V at primary, no hysteresis. The falling edge Open

Secondary threshold is VIL = 135V.

Collector to gate clamp durations that last longer than the

selected Open Secondary Fault Time interval (Table 8)

indicates a failed spark event. When the Open Secondary

Fault Time is exceeded and the Low-voltage Clamp is

enabled, the GDx output will activate the Low-voltage Clamp

shown in figure 16. The Logic for this Low-voltage Clamp is

defined in Figure 9

Table 8. Open Secondary Timer

Spark Command

Bits<b3,b2>

Open Secondary Fault Timer

OSFLT (

μs)

100

LOW-VOLTAGE CLAMP

The Low-voltage Clamp is an internal clamp circuit which

biases the IGBT's gate voltage in order to control the collector

to emitter voltage to VPWR+11V. This technique is used to

dissipate the energy stored in the ignition coil over a longer

period of time than if the internal IGBT clamp were used.

In the open secondary fault condition, all of the stored

energy in the ignition coil is dissipated by the IGBT. This fault

condition requires the use of a higher energy rated IGBT than

would otherwise be needed.

The Low-voltage Clamp spreads out the energy

dissipation over a longer period of time, thus allowing the use

of a lower energy rated IGBTs. The internal low-voltage

clamp is connected between the IGBT's collector (through an

external resistor) and the IGBT's gate. The energy stored in

the ignition coil is dissipated by the IGBT, not the internal

clamp. The internal clamp only provides the bias to the IGBT.

Several logical signals are required as inputs to activate

the GDx Low-voltage Clamp feature. The GDx Low-voltage

Clamp feature may be disabled through bit 4 of the Spark

Command message.

Figure 8.

–

SPI

+−

VPWR

13 V

53 V

GPGD

Low V

Clamp

100 µA

GATE DRIVE

CONTROL

GD1

GD2

GD3

GD0

FB1

FB2

FB3

FB0

–

SPI

Open Secondary

SPI input

SPARK DURATION

Low-voltage Clamp

Figure 9.

OSFLT_En

OSFLT

MaxDwell

MaxDwellEn

IGN Mode

VPWR

OVER-VOLTAGE

OUTEN

SoftShutDnEn

IGN Mode

Activate

Low-voltage

Clamp

Low-voltage Clamp Logic

SOFT SHUTDOWN ENABLE

The soft shutdown feature is enabled via the SPI by

asserting control bit 5 in the Spark Command message.

When enabled, the following events initiate a soft

shutdown control of the gate driver.

• OUTEN = High (Outputs Disabled)

• Over-voltage on VPWR pin

33810 Datasheet(PDF) 21 Page - Freescale Semiconductor, Inc

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