33810 datasheet(24/37 Pages) FREESCALE

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Table 12. Maximum Current DAC Select

DAC Command

Bit<b11,b10,b9,b8>

MAXI

Current (A)

Differential

Voltage (mV

Rs = 20 m

Differential

Voltage (mV

Rs = 40 m

0000

6.0

120

240

0001

7.0

140

280

0010

8.0

160

320

0011

9.0

180

360

0100

10.0

200

400

0101

11.0

220

440

0110

12.0

240

480

0111

13.0

260

520

1000

14.0

280

560

1001

15.0

300

600

1010

16.0

320

640

1011

17.0

340

680

1100

18.0

360

720

1101

19.0

380

760

1110

20.0

400

800

1111

21.0

420

840

Analog Integrated Circuit Device Data

Freescale Semiconductor

33810

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

END OF SPARK FILTER BITS

The ringing at the end of the Spark signatures waveform

can cause erroneous detection of the End of Spark event. To

eliminate the effect of this ringing, a low pass filter with

variable time values can be selected. Four time values for the

low pass filter have been provided with a zero value

indicating that no low pass filtering is to be used. The End of

Spark Filter bits specify a 0, 4µs, 16µs, or 32µs time interval

to sample the spark ignition coil primary current to ignore the

ringing at the end of spark.

Table 13. End of Spark Filter Time Select

End of Spark Filter

Bits<1, 0>

Filter Time

µs

0.0

4.0

16.0

32.0

GENERAL PURPOSE GATE DRIVER MODE

Each gate driver can be individually configured as a

General Purpose Gate Driver (GPGD) and controlled from

the parallel GINx input pins, SPI Driver ON/OFF Command or

may be programmed through the SPI for a specific frequency

and duty cycle output (PWM).

In General Purpose Gate Driver mode the gate drivers

have the following features:

• Gate driver for discrete external MOSFET

• Off state open load detect

• On state short circuit protection

• Programmable drain threshold and duration timer for short

fault detection

• PWM frequency/duty cycle controller

In GPGD Mode the GDx output is a current controlled

output driver with slew rate control, gate to source clamp,

passive pull-down resistor and a drain to gate clamp for

switching inductive loads.

Driver ON/OFF Command

The Driver ON/OFF Command, bits 4 through 7 control

gate drivers that have been Mode Select Command

programmed as GPGD. A logic 1 in bits 4 through 7 will

command the specific output ON. A logic 0 in the appropriate

bit location commands the specific output Off. Also contained

in the Driver ON/OFF Command are SPI control bits for the

integrated LSD output drivers. Further information on LSD

control is provided in the Low Side Injector Driver section of

the data sheet.

NOTE: Gate drivers programmed to IGNITION mode have

parallel input control only, and cannot be turned off and on via

SPI commands.

GPGD Short Threshold Voltage Command

Each GPGD driver is capable of detecting an open load in

the off state and shorted load in the on state. All faults are

reported through the SPI communication. For open load

detection, a current source is placed between the FBx pin

and ground of the IC. An open load fault is reported when the

FBx voltage is less than the 2.5 V threshold. Open load fault

detect threshold is set internally to 2.5 V and may not be

programmed. A shorted load fault is reported when the FBx

pin voltage is greater than the programmed short threshold

voltage.

The short to battery fault threshold voltage of the external

MOSFET is programmed via the GPGD Short Threshold

Voltage Command. Table 14 illustrates the bit pattern to

select a particular threshold. Drain voltages less than the

selected threshold are considered normal operation. Drain

voltages greater than the selected threshold voltage are

considered faulted.

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