LPC1111 datasheet(17/64 Pages) NXP

17 / 64 page

LPC1111_12_13_14

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Product data sheet

Rev. 5 — 22 June 2011

17 of 64

NXP Semiconductors

LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

• In the LPC1111/12/13/14, the NVIC supports 32 vectored interrupts including up to 13

inputs to the start logic from individual GPIO pins.

• Four programmable interrupt priority levels with hardware priority level masking.

• Software interrupt generation.

7.5.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

Any GPIO pin (total of up to 42 pins) regardless of the selected function, can be

programmed to generate an interrupt on a level, or rising edge or falling edge, or both.

7.6 IOCONFIG block

The IOCONFIG block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior

to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

7.7 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs

can be set or cleared in one write operation.

LPC1111/12/13/14 use accelerated GPIO functions:

• GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing

can be achieved.

• Entire port value can be written in one instruction.

Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be

programmed to generate an interrupt on a level, a rising or falling edge, or both.

7.7.1 Features

• Bit level port registers allow a single instruction to set or clear any number of bits in

one write operation.

• Direction control of individual bits.

• All I/O default to inputs with pull-ups enabled after reset with the exception of the

I2C-bus pins PIO0_4 and PIO0_5.

• Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG

block for each GPIO pin (except for pins PIO0_4 and PIO0_5).

• On the LPC111x/101/201/301, all GPIO pins (except PIO0_4 and PIO0_5) are pulled

up to 2.6 V (VDD = 3.3 V) if their pull-up resistor is enabled in the IOCONFIG block.

• On the LPC111x/102/202/302, all GPIO pins (except PIO0_4 and PIO0_5) are pulled

up to 3.3 V (VDD = 3.3 V) if their pull-up resistor is enabled in the IOCONFIG block.

LPC1111 Datasheet(PDF) 17 Page - NXP Semiconductors

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