LPC1111 datasheet(47/64 Pages) NXP

47 / 64 page

LPC1111_12_13_14

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Product data sheet

Rev. 5 — 22 June 2011

47 of 64

NXP Semiconductors

LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

10.5 I/O pins

[1]

Applies to standard port pins and RESET pin.

10.6 I2C-bus

[1]

See the I2C-bus specification UM10204 for details.

[2]

Parameters are valid over operating temperature range unless otherwise specified.

[3]

tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission

and the acknowledge.

[4]

A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the

VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

[5]

Cb = total capacitance of one bus line in pF.

Table 15.

Dynamic characteristic: I/O pins[1]

Tamb = 40 C to +85 C; 3.0 V  VDD  3.6 V.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

rise time

configured as

output

3.0

5.0

fall time

configured as

output

2.5

5.0

Table 16.

Dynamic characteristic: I2C-bus pins[1]

Tamb = 40 C to +85 C.[2]

Symbol

Parameter

Conditions

Min

Max

Unit

fSCL

SCL clock

frequency

Standard-mode

100

kHz

Fast-mode

400

kHz

Fast-mode Plus

MHz

fall time

[4][5][6][7]

of both SDA and

SCL signals

Standard-mode

300

Fast-mode

20 + 0.1

 C

300

Fast-mode Plus

120

tLOW

LOW period of

the SCL clock

Standard-mode

4.7

s

Fast-mode

1.3

s

Fast-mode Plus

0.5

s

tHIGH

HIGH period of

the SCL clock

Standard-mode

4.0

s

Fast-mode

0.6

s

Fast-mode Plus

0.26

s

tHD;DAT

data hold time

[3][4][8]

Standard-mode

s

Fast-mode

s

Fast-mode Plus

s

tSU;DAT

data set-up

time

[9][10]

Standard-mode

250

Fast-mode

100

Fast-mode Plus

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