LPC1111 datasheet(60/64 Pages) NXP

60 / 64 page

LPC1111_12_13_14

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Product data sheet

Rev. 5 — 22 June 2011

60 of 64

NXP Semiconductors

LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

15. Revision history

Table 22.

Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

LPC1111_12_13_14 v.5

20110622

Product data sheet

LPC1111_12_13_14 v.4

Modifications:

• ADC sampling frequency corrected in Table 7 (Table note 7).

• Pull-up level specified in Table 3 to Table 4 and Section 7.7.1.

• Parameter Tcy(clk) corrected on Table 17.

• WWDT for parts LPC111x/102/202/302 added in Section 2 and Section 7.15.

• Programmable open-drain mode for parts LPC111x/102/202/302 added in Section 2

and Section 7.12.

• Condition for parameter Tstg in Table 5 updated.

• Table note 4 of Table 5 updated.

• Section 13 added.

• Removed PLCC44 package information.

LPC1111_12_13_14 v.4

20110210

Product data sheet

LPC1111_12_13_14 v.3

Modifications:

• Power consumption graphs added for parts LPC111x/102/202/302 (Figure 13 to

Figure 17).

• Parameter Vhys for I2C bus pins: typical value corrected Vhys = 0.05VDD in Table 7.

• Typical value for parameter Nendu added in Table 12 “Flash characteristics”.

• I2C-bus pins configured as standard mode pins, parameter IOL changed to 3.5 mA

(minimum) for 2.0 V

 V

DD  3.6 V.

• Section 11.6 “ElectroMagnetic Compatibility (EMC)” added.

• Power-up characterization added (Section 10.1 “Power-up ramp conditions”).

LPC1111_12_13_14 v.3

20101110

Product data sheet

LPC1111_12_13_14 v.2

Modifications:

• Parts LPC111x/102/202/302 added (LPC1100L series).

• Power consumption data for parts LPC111x/102/202/302 added in Table 7.

• PLL output frequency limited to 100 MHz in Section 7.15.2.

• Description of RESET and WAKEUP functions updated in Section 6.

• WDT description updated in Section 7.14. The WDT is a 24-bit timer.

• Power profiles added to Section 2 and Section 7 for parts LPC111x/102/202/302.

LPC1111_12_13_14 v.2

20100818

Product data sheet

LPC1111_12_13_14 v.1

Modifications:

• VESD limit changed to 6500 V (min) /+6500 V (max) in Table 6.

• tDS updated for SPI in master mode (Table 17).

• Deep-sleep mode functionality changed to allow BOD and watchdog oscillator as the

only analog blocks allowed to remain running in Deep-sleep mode (Section 7.15.5.3).

• VDD range changed to 3.0 V  VDD  3.6 V in Table 15.

• Reset state of pins and start logic functionality added in Table 3 to Table 5.

• Section 7.16.1 added.

• Section “Memory mapping control” removed.

• VOH and IOH specifications updated for high-drive pins in Table 7.

• Section 9.4 added.

LPC1111_12_13_14 v.1

20100416

Product data sheet

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