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LPC1850 Datasheet(PDF) 113 Page - NXP Semiconductors |
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LPC1850 Datasheet(HTML) 113 Page - NXP Semiconductors |
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113 / 142 page ![]() LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 113 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 11.9 SD/MMC Table 20. Dynamic characteristics: SD/MMC Tamb = 40 C to 85 C, VDD(REG)(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Conditions Min Max Unit fclk clock frequency on pin SD_CLK; data transfer mode - 25 MHz on pin SD_CLK; identification mode 25 MHz tsu(D) data input set-up time on pins SD_CMD, SD_DATn as inputs 6- ns th(D) data input hold time on pins SD_CMD, SD_DATn as inputs 6- ns td(QV) data output valid delay time on pins SD_CMD, SD_DATn as outputs -23 ns th(Q) data output hold time on pins SD_CMD, SD_DATn as outputs 3.5 - ns Fig 41. SD/MMC timing 002aag204 SD_CLK SD_DATn (O) SD_DATn (I) td(QV) th(D) tsu(D) Tcy(clk) th(Q) SD_CMD (O) SD_CMD (I) |
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