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LPC1850 Datasheet(PDF) 109 Page - NXP Semiconductors

Part # LPC1850
Description  32-bit ARM Cortex-M3 MCU; up to 200 kB SRAM; Ethernet, two High-speed USB, LCD, and external memory controller
PDF  142 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC1850 Datasheet(HTML) 109 Page - NXP Semiconductors

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LPC1850_30_20_10
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Preliminary data sheet
Rev. 2.2 — 9 September 2011
109 of 142
NXP Semiconductors
LPC1850/30/20/10
32-bit ARM Cortex-M3 microcontroller
td(WV)
write valid delay time
<tbd>
<tbd>
<tbd>
ns
th(W)
write hold time
<tbd>
<tbd>
<tbd>
ns
td(GV)
output enable valid delay time
<tbd>
<tbd>
<tbd>
ns
th(G)
output enable hold time
<tbd>
<tbd>
<tbd>
ns
td(AV)
address valid delay time
<tbd>
<tbd>
<tbd>
ns
th(A)
address hold time
<tbd>
<tbd>
<tbd>
ns
Read cycle parameters
tsu(D)
data input set-up time
<tbd>
<tbd>
<tbd>
ns
th(D)
data input hold time
<tbd>
<tbd>
<tbd>
ns
Write cycle parameters
td(QV)
data output valid delay time
<tbd>
<tbd>
<tbd>
ns
th(Q)
data output hold time
<tbd>
<tbd>
<tbd>
ns
Table 16.
Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00 …continued
CL =30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = <tbd>.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Table 17.
Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01
CL =30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = <tbd>.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Common to read and write cycles
td(SV)
chip select valid delay time
<tbd>
<tbd>
<tbd>
ns
th(S)
chip select hold time
<tbd>
<tbd>
<tbd>
ns
td(RASV)
row address strobe valid delay time
<tbd>
<tbd>
<tbd>
ns
th(RAS)
row address strobe hold time
<tbd>
<tbd>
<tbd>
ns
td(CASV)
column address strobe valid delay time
<tbd>
<tbd>
<tbd>
ns
th(CAS)
column address strobe hold time
<tbd>
<tbd>
<tbd>
ns
td(WV)
write valid delay time
<tbd>
<tbd>
<tbd>
ns
th(W)
write hold time
<tbd>
<tbd>
<tbd>
ns
td(GV)
output enable valid delay time
-
-
-
ns
th(G)
output enable hold time
-
-
-
ns
td(AV)
address valid delay time
<tbd>
<tbd>
<tbd>
ns
th(A)
address hold time
<tbd>
<tbd>
<tbd>
ns
Read cycle parameters
tsu(D)
data input set-up time
<tbd>
<tbd>
<tbd>
ns
th(D)
data input hold time
<tbd>
<tbd>
<tbd>
ns
Write cycle parameters
td(QV)
data output valid delay time
<tbd>
<tbd>
<tbd>
ns
th(Q)
data output hold time
<tbd>
<tbd>
<tbd>
ns



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