LPC1850 datasheet(112/142 Pages) NXP

112 / 142 page

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Preliminary data sheet

Rev. 2.2 — 9 September 2011

112 of 142

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

[1]

Output drivers can drive a load

 25 pF accommodating over 12 inch of PCB trace and the input

capacitance of the receiving device.

[2]

Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or

output level.

tsu

set-up time

for ENET_TXDn, ENET_TX_EN,

ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

[1][2]

<tbd>

hold time

for ENET_TXDn, ENET_TX_EN,

ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

[1][2]

<tbd>

MII mode

fclk

clock frequency

for ENET_TX_CLK

[1]

<tbd>

MHz



clk

clock duty cycle

[1]

<tbd>

tsu

set-up time

for ENET_TXDn, ENET_TX_EN,

ENET_TX_ER

[1][2]

<tbd>

hold time

for ENET_TXDn, ENET_TX_EN,

ENET_TX_ER

[1][2]

<tbd>

fclk

clock frequency

for ENET_RX_CLK

[1]

<tbd>

MHz



clk

clock duty cycle

[1]

<tbd>

tsu

set-up time

for ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

[1][2]

<tbd>

hold time

for ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

[1][2]

<tbd>

Fig 40. Ethernet timing

Table 19.

Dynamic characteristics: Ethernet

Tamb = 40 C to 85 C, VDD(REG)(3V3) = <tbd>.

Symbol Parameter

Conditions

Min

Max

Unit

002aag210

tsu

ENET_RX_CLK

ENET_TX_CLK

ENET_RXD[n]

ENET_RX_DV

ENET_RX_ER

ENET_TXD[n]

ENET_TX_EN

ENET_TX_ER

LPC1850 Datasheet(PDF) 112 Page - NXP Semiconductors

LPC1850 Datasheet(HTML) 112 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL