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AM3359 Datasheet(PDF) 102 Page - Texas Instruments

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Part # AM3359
Description  AM335x ARM짰 Cortex??A8 Microprocessors (MPUs)
PDF  195 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM3359 Datasheet(HTML) 102 Page - Texas Instruments

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AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717B
– OCTOBER 2011 – REVISED JANUARY 2012
www.ti.com
5
Peripheral Information and Timings
The AM335x device contains many peripheral interfaces. In order to reduce package size and cost while
maintaining maximum functionality, many of the AM335x terminals can multiplex up to eight signal
functions. Although there are many combinations of pin multiplexing that are possible, only a certain
number of sets, called IO sets, are valid due to timing limitations. These valid IO sets were carefully
chosen to provide many possible application scenarios for the user.
Texas Instruments has developed a Windows application called Pin Mux Utility that helps a system
designer select the appropriate pin-multiplexing configuration for their AM335x-based product design. This
tool provides a way to select valid IO sets of specific peripheral interfaces to ensure that the
pin-multiplexing configuration selected for a design only uses valid IO sets supported by the AM335x
device.
5.1
Parameter Information
5.1.1
Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routings. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external
logic hardware such as buffers may be used to compensate any timing differences.
For the mDDR(LPDDR)/DDR2/DDR3 memory interface, it is not necessary to use the IBIS models to
analyze timing characteristics. TI provides a PCB routing rules solution that describes the routing rules to
ensure the mDDR(LPDDR)/DDR2/DDR3 memory interface timings are met.
5.2
Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
102
Peripheral Information and Timings
Copyright
© 2011–2012, Texas Instruments Incorporated
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Product Folder Link(s): AM3359 AM3358 AM3357 AM3356 AM3354 AM3352



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