AM3359 datasheet(103/195 Pages) TI

103 / 195 page

GMII[x]_RXCLK

AM3359, AM3358, AM3357

AM3356, AM3354, AM3352

www.ti.com

SPRS717B

– OCTOBER 2011 – REVISED JANUARY 2012

5.3

Ethernet Media Access Controller (EMAC)/Switch

5.3.1

Ethernet MAC/Switch Electrical Data/Timing

The Ethernet MAC/Switch implemented in the AM335x device supports GMII mode, but the AM335x

design does not pin out 9 of the 24 GMII signals. This was done to reduce the total number of package

terminals. Therefore, the AM335x device does not support GMII mode. MII mode is supported with the

remaining GMII signals.

The AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (literature number

SPRUH73) and this document may reference internal signal names when discussing peripheral input and

output signals since many of the AM335x package terminals can be multiplexed to one of several

peripheral signals. For example, the AM335x terminal names for port 1 of the Ethernet MAC/Switch have

been changed from GMII to MII to indicate their Mode 0 function, but the internal signal is named GMII.

However, documents that describe the Ethernet switch reference these signals by their internal signal

name. For a cross-reference of internal signal names to terminal names, see Table 2-7.

Operation of the Ethernet MAC/Switch is not supported for OPP50.

Table 5-1. Ethernet MAC/Switch Timing Conditions

TIMING CONDITION PARAMETER

MIN

TYP

MAX

UNIT

Input Conditions

Input signal rise time

1(1)

5(1)

Input signal fall time

1(1)

5(1)

Output Condition

CLOAD

Output load capacitance

(1) Except when specified otherwise.

5.3.1.1

Ethernet MAC/Switch MII Electrical Data/Timing

Table 5-2. Timing Requirements for GMII[x]_RXCLK - MII Mode

(see Figure 5-1)

10 Mbps

100 Mbps

NO.

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

tc(RX_CLK)

Cycle time, RX_CLK

399.96

400.04

39.996

40.004

tw(RX_CLKH)

Pulse Duration, RX_CLK high

140

260

tw(RX_CLKL)

Pulse Duration, RX_CLK low

140

260

tt(RX_CLK)

Transition time, RX_CLK

Figure 5-1. GMII[x]_RXCLK Timing - MII Mode

Peripheral Information and Timings

103

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