AM3359 datasheet(110/195 Pages) TI

110 / 195 page

AM3359, AM3358, AM3357

AM3356, AM3354, AM3352

SPRS717B

– OCTOBER 2011 – REVISED JANUARY 2012

www.ti.com

5.4

External Memory Interfaces

The device includes the following external memory interfaces:

•

General-purpose memory controller (GPMC)

•

mDDR(LPDDR)/DDR2/DDR3 Memory Interface (EMIF)

5.4.1

General-Purpose Memory Controller (GPMC)

NOTE

For more information, see the Memory Subsystem/General-Purpose Memory Controller

section of the AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference

Manual (literature number SPRUH73).

The GPMC is the unified memory controller used to interface external memory devices such as:

•

Asynchronous SRAM-like memories and ASIC devices

•

Asynchronous page mode and synchronous burst NOR flash

•

NAND flash

5.4.1.1

GPMC/NOR Flash

—Synchronous Mode

Synchronous mode is not supported for OPP50.

Table 5-14 and Table 5-15 assume testing over the recommended operating conditions and electrical

characteristic conditions below (see Figure 5-12 through Figure 5-16).

Table 5-13. GPMC/NOR Flash Timing Conditions

—Synchronous Mode

TIMING CONDITION PARAMETER

MIN

TYP

MAX

UNIT

Input Conditions

Input signal rise time

Input signal fall time

Output Condition

CLOAD

Output load capacitance

Table 5-14. GPMC/NOR Flash Timing Requirements

—Synchronous Mode

OPP100

NO.

PARAMETER

UNIT

MIN

MAX

F12

tsu(dV-clkH)

Setup time, input data gpmc_ad[15:0] valid before output clock gpmc_clk

3.2

high

F13

th(clkH-dV)

Hold time, input data gpmc_ad[15:0] valid after output clock gpmc_clk high

2.5

F21

tsu(waitV-clkH)

Setup time, input wait gpmc_wait[x](1) valid before output clock gpmc_clk

3.2

high

F22

th(clkH-waitV)

Hold time, input wait gpmc_wait[x](1) valid after output clock gpmc_clk high

2.5

(1) In gpmc_wait[x], x is equal to 0 or 1.

110

Peripheral Information and Timings

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