AM3359 datasheet(111/195 Pages) TI

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AM3359, AM3358, AM3357

AM3356, AM3354, AM3352

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SPRS717B

– OCTOBER 2011 – REVISED JANUARY 2012

Table 5-15. GPMC/NOR Flash Switching Characteristics

—Synchronous Mode(2)

NO.

PARAMETER

OPP100

UNIT

MIN

MAX

1 / tc(clk)

Frequency(15), output clock gpmc_clk

100

MHz

tw(clkH)

Typical pulse duration, output clock gpmc_clk high

0.5P(12)

tw(clkL)

Typical pulse duration, output clock gpmc_clk low

0.5P(12)

tdc(clk)

Duty cycle error, output clock gpmc_clk

–500

500

tJ(clk)

Jitter standard deviation(16), output clock gpmc_clk

33.33

tR(clk)

Rise time, output clock gpmc_clk

tF(clk)

Fall time, output clock gpmc_clk

tR(do)

Rise time, output data gpmc_ad[15:0]

tF(do)

Fall time, output data gpmc_ad[15:0]

td(clkH-csnV)

Delay time, output clock gpmc_clk rising edge to output chip

F(6)

– 2.2

F(6) + 4.5

select gpmc_csn[x](11) transition

td(clkH-csnIV)

Delay time, output clock gpmc_clk rising edge to output chip

E(5)

– 2.2

E(5) + 4.5

select gpmc_csn[x](11) invalid

td(aV-clk)

Delay time, output address gpmc_a[27:1] valid to output clock

B(2)

– 4.5

B(2) + 2.3

gpmc_clk first edge

td(clkH-aIV)

Delay time, output clock gpmc_clk rising edge to output address

–2.3

4.5

gpmc_a[27:1] invalid

td(be[x]nV-clk)

Delay time, output lower byte enable/command latch enable

B(2)

– 1.9

B(2) + 2.3

gpmc_be0n_cle, output upper byte enable gpmc_be1n valid to

output clock gpmc_clk first edge

td(clkH-be[x]nIV)

Delay time, output clock gpmc_clk rising edge to output lower

D(4)

– 2.3

D(4) + 1.9

byte enable/command latch enable gpmc_be0n_cle, output

upper byte enable gpmc_be1n invalid

td(clkH-advn)

Delay time, output clock gpmc_clk rising edge to output address

G(7) + 2.3

G(7) + 4.5

valid/address latch enable gpmc_advn_ale transition

td(clkH-advnIV)

Delay time, output clock gpmc_clk rising edge to output address

D(4)

– 2.3

D(4) + 3.5

valid/address latch enable gpmc_advn_ale invalid

F10

td(clkH-oen)

Delay time, output clock gpmc_clk rising edge to output enable

H(8)

– 2.3

H(8) + 3.5

gpmc_oen transition

F11

td(clkH-oenIV)

Delay time, output clock gpmc_clk rising edge to output enable

E(5)

– 2.3

E(5) + 3.5

gpmc_oen invalid

F14

td(clkH-wen)

Delay time, output clock gpmc_clk rising edge to output write

I(9)

– 2.3

I(9) + 4.5

enable gpmc_wen transition

F15

td(clkH-do)

Delay time, output clock gpmc_clk rising edge to output data

J(10)

– 2.3

J(10) + 1.9

gpmc_ad[15:0] transition

F17

td(clkH-be[x]n)

Delay time, output clock gpmc_clk rising edge to output lower

J(10)

– 2.3

J(10) + 1.9

byte enable/command latch enable gpmc_be0n_cle transition

F18

tw(csnV)

Pulse duration, output chip select gpmc_csn[x](11)

Read

A(1)

low

Write

A(1)

F19

tw(be[x]nV)

Pulse duration, output lower byte enable/command

Read

C(3)

latch enable gpmc_be0n_cle, output upper byte

Write

C(3)

enable gpmc_be1n low

F20

tw(advnV)

Pulse duration, output address valid/address latch

Read

K(13)

enable gpmc_advn_ale low

Write

K(13)

(1) For single read: A = (CSRdOffTime

– CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)

For burst read: A = (CSRdOffTime

– CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)

For burst write: A = (CSWrOffTime

– CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)

With n being the page burst access number.

(2) B = ClkActivationTime * GPMC_FCLK(14)

(3) For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK (14)

For burst read: C = (RdCycleTime + (n

– 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)

For burst write: C = (WrCycleTime + (n

– 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)

With n being the page burst access number.

(4) For single read: D = (RdCycleTime

– AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)

Peripheral Information and Timings

111

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