ADS1292 datasheet(33/69 Pages) TI

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START

Device

CLK

DRDY

START

CLK

START

Device

CLK

DRDY

START

CLK

DRDY

Note 1

Note 2

START

DRDY

SCLK

DIN

DOUT

ADS1292

(Device0)

START

DRDY

SCLK

DIN

DOUT

ADS1292R

(Device1)

START

(1)

CLK

INT

GPO0

GPO1

SCLK

MOSI

HostProcessor

MISO

CLK

ADS1291

ADS1292

ADS1292R

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SBAS502A – DECEMBER 2011 – REVISED MARCH 2012

When using multiple devices, the devices can be synchronized with the START signal. The delay from START to

the DRDY signal is fixed for a fixed data rate (see the START subsection of the SPI Interface section for more

details on the settling times). Figure 41 shows the behavior of two devices when synchronized with the START

signal.

(1) Start pulse must be at least one tMOD cycle wide.

(2) Settling time number uncertainty is one tMOD cycle.

Figure 41. Synchronizing Multiple Converters

Standard Mode

Figure 42 shows a configuration with two devices cascaded together. One of the devices is an ADS1292R (two-

channel with RESP) and the other is an ADS1292 (two-channel). Together, they create a system with four

channels. DOUT, SCLK, and DIN are shared. Each device has its own chip select. When a device is not selected

by the corresponding CS being driven to logic 1, the DOUT of this device is high-impedance. This structure

allows the other device to take control of the DOUT bus.

Figure 42. Multiple Device Configurations

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ADS1292 Datasheet(PDF) 33 Page - Texas Instruments

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