RM48L540 datasheet(101/152 Pages) TI1

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RM48L940

RM48L740

RM48L540

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SPNS175

– SEPTEMBER 2011

Table 4-36. Reset/Abort/Error Sources (continued)

ESM HOOKUP

ERROR SOURCE

SYSTEM MODE

ERROR RESPONSE

group.channel

eFuse Controller - Any bit set in the error status register

User/Privilege

ESM

1.40

eFuse Controller self-test error

User/Privilege

ESM

1.41

WINDOWED WATCHDOG

WWD Non-Maskable Interrupt exception

n/a

ESM

2.24

ERRORS REFLECTED IN THE SYSESR REGISTER

Power-Up Reset

n/a

Reset

n/a

Oscillator fail / PLL slip(2)

n/a

Reset

n/a

Watchdog exception

n/a

Reset

n/a

CPU Reset (driven by the CPU STC)

n/a

Reset

n/a

Software Reset

n/a

Reset

n/a

External Reset

n/a

Reset

n/a

(2)

Oscillator fail/PLL slip can be configured in the system register (SYS.PLLCTL1) to generate a reset.

4.20 Digital Windowed Watchdog

This device includes a digital windowed watchdog (DWWD) module that protects against runaway code

execution.

The DWWD module allows the application to configure the time window within which the DWWD module

expects the application to service the watchdog. A watchdog violation occurs if the application services the

watchdog outside of this window, or fails to service the watchdog at all. The application can choose to

generate a system reset or a non-maskable interrupt to the CPU in case of a watchdog violation.

The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog

can only be disabled upon a system reset.

System Information and Electrical Specifications

101

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