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HCLK

DMMCLK

DMMSYNC

DMMDATA

DMMnENA

D00

D01

D10

D11

D20

D21

D30

D31

D40

D41

D50

RM48L940

RM48L740

RM48L540

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SPNS175

– SEPTEMBER 2011

Table 4-47. DMMDATA Timing

Parameter

MIN

Description

tssu(DMM)

2ns

SYNC active to clk falling edge setup time

tsh(DMM)

3ns

clk falling edge to SYNC deactive hold time

tdsu(DMM)

2ns

DATA to clk falling edge setup time

tdh(DMM)

3ns

clk falling edge to DATA hold time

Figure 4-29. DMMnENA Timing

Figure 4-29 shows a case with 1 DMM packet per 2 DMMCLK cycles (Mode = Direct Data Mode, data

width = 8, portwidth = 4) where none of the packets received by the DMM are sent out, leading to filling up

of the internal buffers. The DMMnENA signal is shown asserted, after the first two packets have been

received and synchronised to the HCLK domain. Here, the DMM has the capacity to accept packets D4x,

D5x, D6x, D7x. Packet D8 would result in an overflow. Once DMMnENA is asserted, the DMM expects to

stop receiving packets after 4 HCLK cycles; once DMMnENA is de-asserted, the DMM can handle

packets immediately (after 0 HCLK cycles).

System Information and Electrical Specifications

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