WM8758B datasheet(37/90 Pages) WOLFSON

37 / 90 page

Production Data

WM8758B

PD, Rev 4.4, January 2012

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R15

Left channel

ADC Digital

Volume

7:0

ADCLVOL

[7:0]

11111111

( 0dB )

Left ADC Digital Volume Control

0000 0000 = Digital Mute

0000 0001 = -127dB

0000 0010 = -126.5dB

... 0.5dB steps up to

1111 1111 = 0dB

ADCVU

Not

latched

ADC left and ADC right volume do not

update until a 1 is written to ADCVU (in

reg 15 or 16)

R16

Right channel

ADC Digital

Volume

7:0

ADCRVOL

[7:0]

11111111

( 0dB )

Right ADC Digital Volume Control

0000 0000 = Digital Mute

0000 0001 = -127dB

0000 0010 = -126.5dB

... 0.5dB steps up to

1111 1111 = 0dB

ADCVU

Not

latched

ADC left and ADC right volume do not

update until a 1 is written to ADCVU (in

reg 15 or 16)

Table 17 ADC Digital Volume Control

INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC)

The WM8758B has an automatic PGA gain control circuit, which can function as an input peak limiter

or as an automatic level control (ALC).

In input peak limiter mode (ALCMODE bit = 1), a digital peak detector detects when the input signal

goes above a predefined level and will ramp the PGA gain down to prevent the signal becoming too

large for the input range of the ADC. When the signal returns to a level below the threshold, the PGA

gain is slowly returned to its starting level. The peak limiter cannot increase the PGA gain above its

static level.

Figure 20 Input Peak Limiter Operation

WM8758B Datasheet(PDF) 37 Page - Wolfson Microelectronics plc

WM8758B Datasheet(HTML) 37 Page - Wolfson Microelectronics plc

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