WM8758B datasheet(68/90 Pages) WOLFSON

68 / 90 page

WM8758B

Production Data

PD, Rev 4.4, January 2012

AUDIO SAMPLE RATES

The WM8758B filter characteristics for the ADCs and the DACs are set using the SR register bits.

The cutoffs for the digital filters and the ALC attack/decay times stated are determined using these

values and assume a 256fs master clock rate.

If a sample rate that is not explicitly supported by the SR register settings is required then the closest

SR value to that sample rate should be chosen, the filter characteristics and the ALC attack, decay

and hold times will scale appropriately.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Additional

Control

3:1

000

Approximate sample rate (configures the

coefficients for the internal digital filters):

000 = 48kHz

001 = 32kHz

010 = 24kHz

011 = 16kHz

100 = 12kHz

101 = 8kHz

110-111 = reserved

Table 46 Sample Rate Control

MASTER CLOCK AND PHASE LOCKED LOOP (PLL)

The WM8758B has an on-chip phase-locked loop (PLL) circuit that can be used to:

Generate master clocks for the WM8758B audio functions from another external clock, e.g. in

telecoms applications.

Generate and output (on pin CSB/GPIO1) a clock for another part of the system that is derived from

an existing audio master clock.

Figure 40 shows the PLL and internal clocking on the WM8758B.

The PLL can be enabled or disabled by the PLLEN register bit.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Power

management 1

PLLEN

PLL enable

0 = PLL off

1 = PLL on

Table 47 PLLEN Control Bit

WM8758B Datasheet(PDF) 68 Page - Wolfson Microelectronics plc

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