WM8758B datasheet(65/90 Pages) WOLFSON

65 / 90 page

Production Data

WM8758B

PD, Rev 4.4, January 2012

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Clock

Generation

Control

Sets the chip to be master over LRC and

BCLK

0 = BCLK and LRC clock are inputs

1 = BCLK and LRC clock are outputs

generated by the WM8758B (MASTER)

4:2

BCLKDIV

000

Configures the BCLK and LRC output

frequency, for use when the chip is

master over BCLK.

000 = divide by 1 (BCLK=SYSCLK)

001 = divide by 2 (BCLK=SYSCLK/2)

010 = divide by 4

011 = divide by 8

100 = divide by 16

101 = divide by 32

110 = reserved

111 = reserved

7:5

MCLKDIV

010

Sets the scaling for either the MCLK or

PLL clock output (under control of

CLKSEL)

000 = divide by 1

001 = divide by 1.5

010 = divide by 2

011 = divide by 3

100 = divide by 4

101 = divide by 6

110 = divide by 8

111 = divide by 12

CLKSEL

Controls the source of the clock for all

internal operation:

0 = MCLK

1 = PLL output

Table 43 Clock Control

The CLKSEL bit selects the internal source of the Master clock from the PLL (MCLK=1) or from

MCLK (MCLKSEL=0). When the internal clock is switched from one source to another using the

CLKSEL bit, the clock originally selected must generate at least one falling edge after CLKSEL has

changed for the switching of clocks to be successful.

EXAMPLE:

If the PLL is the current source of the internal clock (CLKSEL=1) and it is required to switch to the

MCLK, change CLKSEL to select MCLK (CLKSEL=0) and then disable PLL (PLLEN=0).

LOOPBACK

Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data

from the ADC audio interface is fed directly into the DAC data input.

COMPANDING

The WM8758B supports A-law and

-law companding on both transmit (ADC) and receive (DAC)

sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate

value to the DAC_COMP or ADC_COMP register bits respectively.

WM8758B Datasheet(PDF) 65 Page - Wolfson Microelectronics plc

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