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WM8758B Datasheet(PDF) 74 Page - Wolfson Microelectronics plc

Part # WM8758B
Description  Stereo CODEC with Headphone Driver and Line Out
PDF  90 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8758B Datasheet(HTML) 74 Page - Wolfson Microelectronics plc

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WM8758B
Production Data
w
PD, Rev 4.4, January 2012
74
Figure 41 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8758B supports software control via a 2-wire serial bus. Many devices can be controlled by
the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit
address of each register in the WM8758B).
The WM8758B operates as a slave device only. The controller indicates the start of data transfer with
a high to low transition on SDIN while SCLK remains high. This indicates that a device address and
data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight
bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the
address of the WM8758B, the WM8758B responds by pulling SDIN low on the next clock pulse
(ACK). If the address is not equalized or the R/W bit is ‘1’ when operating in write only mode, the
WM8758B returns to the idle condition and waits for a new start condition and valid address.
During a write, once the WM8758B has acknowledged a correct address, the controller sends the
first byte of control data (B15 to B8, i.e. the WM8758B register address plus the first bit of register
data). The WM8758B then acknowledges the first data byte by driving SDIN low for one clock cycle.
The controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of
register data), and the WM8758B acknowledges again by pulling SDIN low.
Transfer is complete when there is a low to high transition on SDIN while SCLK is high. After a
complete sequence the WM8758B returns to the idle state and waits for another start condition. If a
start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN
changes while SCLK is high), the control interface returns to the idle condition.
SDIN
SCLK
register address and
1st register data bit
DEVICE ADDRESS
(7 BITS)
RD / WR
BIT
ACK
(LOW)
CONTROL BYTE 1
(BITS 15 TO 8)
CONTROL BYTE 1
(BITS 7 TO 0)
remaining 8 bits of
register data
STOP
START
ACK
(LOW)
ACK
(LOW)
Figure 42 2-Wire Serial Control Interface
In 2-wire mode the WM8758B has a fixed device address, 0011010.
In 2-wire mode the CSB/GPIO1 pin controls the inversion of the HP_COM and LINE_COM register
bits. When CSB/GPIO1 is set, these register bits are inverted (providing CSB/GPIO1 is not
configured as a GPIO). See the section titled COMMON MODE DEFAULT for more details.
RESETTING THE CHIP
The WM8758B can be reset by performing a write of any value to the software reset register (address
0h). This will cause all register values to be reset to their default values. In addition to this there is a
Power-On Reset (POR) circuit which ensures that the registers are initially set to default when the
device is powered up.



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