WM8310 datasheet(147/291 Pages) WOLFSON

147 / 291 page

Pre-Production

WM8310

PP, May 2012, Rev 3.1

147

ADDRESS

BIT

LABEL

DESCRIPTION

7:4

IM_AUXADC_DCOMPn_EI

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Note: n is a number between 1 and 4 that identifies the individual Comparator.

Table 91 AUXADC Interrupts

23.2.9

POWER PATH MANAGEMENT INTERRUPTS

The primary PPM_INT interrupt comprises three secondary interrupts as described in Section 17.5.

The secondary interrupt bits are defined in Table 92.

Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt

event is masked and does not trigger a PPM_INT interrupt. The secondary interrupt bits in R16401

(4011h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked

by default.

ADDRESS

BIT

LABEL

DESCRIPTION

R16401

(4011h)

Interrupt Status

PPM_SYSLO_EINT

Power Path SYSLO interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

PPM_PWR_SRC_EINT

Power Path Source interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

PPM_USB_CURR_EINT

Power Path USB Current interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

R16409

(4019h)

Interrupt Status

1 Mask

IM_PPM_SYSLO_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_PPM_PWR_SRC_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_PPM_USB_CURR_EIN

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Table 92 Power Path Management Interrupts

23.2.10 CURRENT SINK INTERRUPTS

The primary CS_INT interrupt comprises two secondary interrupts as described in Section 16.3. The

secondary interrupt bits are defined in Table 93.

Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt

event is masked and does not trigger a CS_INT interrupt. The secondary interrupt bits in R16402

(4012h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked

by default.

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