WM8310 datasheet(158/291 Pages) WOLFSON

158 / 291 page

WM8310

Pre-Production

PP, May 2012, Rev 3.1

158

25 WATCHDOG TIMER

The WM8310 includes a Watchdog Timer designed to detect a possible software fault condition

where the host processor has locked up. The Watchdog Timer is a free-running counter driven by the

internal RC oscillator.

The Watchdog Timer is enabled by default; it can be enabled or disabled by writing to the

WDOG_ENA register bit. The Watchdog behaviour in SLEEP is configurable; it can either be set to

continue as normal or to be disabled. The Watchdog behaviour in SLEEP is determined by the

WDOG_SLPENA bit.

The watchdog timer duration is set using WDOG_TO. The watchdog timer can be halted for debug

purposes using the WDOG_DEBUG bit.

The Watchdog reset source is selectable between Software and Hardware triggers. (Note that the de-

selected reset source has no effect.) If the Watchdog is not reset within a programmable timeout

period, this is interpreted by the WM8310 as a fault condition. The Watchdog Timer then either

triggers a Device Reset, or issues a WAKE request or raises an Interrupt. The action taken is

determined by the WDOG_PRIMACT register field.

If the Watchdog is not reset within a further timeout period of the Watchdog counter, a secondary

action is triggered. The secondary action taken at this point is determined by the WDOG_SECACT

The Watchdog reset source is selected using the WDOG_RST_SRC register bit. When Software

WDOG reset source is selected, the Watchdog is reset by writing a ‘1’ to the WDOG_RESET field.

When Hardware WDOG reset source is selected, the Watchdog is reset by toggling a GPIO pin that

has been configured as a Watchdog Reset Input (see Section 21).

If a Device Reset is triggered by the watchdog timeout, the WM8310 asserts the RESET

¯¯¯¯¯¯ pin, resets

the internal control registers (excluding the RTC) and initiates a start-up sequence. The Watchdog

Timer is not automatically reset as part of the Device Reset; the Watchdog must be reset by the host

application following the Device Reset.

Note that, following a Device Reset, the action taken on subsequent timeout of the Watchdog Timer

will be determined by the WDOG_PRIMACT register. If the watchdog timeout fault persists, then a

maximum of 6 Device Reset attempts will be made. See Section 24. If the watchdog timeout occurs

more than 6 times, the WM8310 will remain in the OFF state until the next valid ON state transition

event occurs.

Note that the Watchdog control registers are locked by the WM8310 User Key. These registers can

only be changed by writing the appropriate code to the Security register, as described in Section 12.4.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R16388

(4004h)

Watchdog

WDOG_ENA

Watchdog Timer Enable

0 = Disabled

1 = Enabled (enables the watchdog; does

not reset it)

Protected by user key

WDOG_DEBU

Watchdog Pause

0 = Disabled

1 = Enabled (halts the Watchdog timer for

system debugging)

Protected by user key

WDOG_RST_S

Watchdog Reset Source

0 = Hardware only

1 = Software only

Protected by user key

WDOG_SLPE

Watchdog SLEEP Enable

0 = Disabled

1 = Controlled by WDOG_ENA

Protected by user key

WM8310 Datasheet(PDF) 158 Page - Wolfson Microelectronics plc

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