WM8310 datasheet(156/291 Pages) WOLFSON

156 / 291 page

WM8310

Pre-Production

PP, May 2012, Rev 3.1

156

24.4 SUPPLY VOLTAGE MONITORING

The WM8310 includes a number of mechanisms to prevent the system from starting up, or to force it

to shut down, when the power sources are critically low.

The power supply configuration for the WM8310 is described in Section 17. The chip automatically

chooses the most suitable supply, selecting between a Wall adapter supply, USB or Battery. The

preferred source is routed to the SYSVDD pin, to which the other power management circuits would

typically be connected. The SYSVDD voltage is monitored internally, as described below.

The internal regulator LDO12 is powered from an internal domain equivalent to SYSVDD and

generates an internal supply (VPMIC) to support various “always-on” functions. In the absence of the

Wall, USB or Battery supplies, LDO12 can be powered from a backup supply. (Note that SYSVDD is

not maintained by the backup supply.) The VPMIC monitoring function controls the Power-On Reset

circuit, which sets the threshold below which the WM8310 cannot operate.

The operation of the VPMIC monitoring circuit is illustrated in Figure 31. The internal signal PORRST

¯¯¯¯¯¯¯

is governed by the VPOR thresholds. These determine when the WM8310 is kept in the NO POWER

state. The internal signal PMICRST

¯¯¯¯¯¯¯¯ is governed by the VRES thresholds. These determine when the

WM8310 is kept in the BACKUP state.

The VPMIC monitoring thresholds illustrated in Figure 31 are fixed. The voltage levels are defined in

the Electrical Characteristics - see Section 7.5.

Figure 31 VPMIC Monitoring

The operation of the SYSVDD monitoring circuit is illustrated in Figure 32. The VSHUTDOWN threshold is

the voltage below which the WM8310 forces an OFF transition. This threshold voltage is fixed and is

defined in the Electrical Characteristics - see Section 7.5.

The VSYSOK threshold is the level at which the internal signal SYSOK is asserted. Any ON request will

be inhibited if SYSOK is not set. The VSYSOK threshold can be set using the SYSOK_THR register field

in accordance with the minimum voltage requirements of the application. Note that a hysteresis

margin is added to the SYSOK_THR setting; see Section 7.5 for details.

The VSYSLO threshold is the level at which the internal signal SYSLO is asserted. This indicates a

SYSVDD undervoltage condition, at which a selectable response can be initiated. The VSYSLO

threshold can be set using the SYSLO_THR register field. The action taken under this undervoltage

condition is selected using the SYSLO_ERR_ACT register field, as defined in Table 101. An Interrupt

event is associated with the SYSLO condition - see Section 17.5.

WM8310 Datasheet(PDF) 156 Page - Wolfson Microelectronics plc