WM8351 datasheet(136/330 Pages) WOLFSON

136 / 330 page

WM8351

Production Data

PD, April 2012, Rev 4.5

136

The LDO Regulators can also be controlled by the device HIBERNATE bit, or by hardware input

signals L_PWR1, L_PWR2 and L_PWR3. Several GPIO pins can be assigned as L_PWR pins. Each

Regulator can be assigned to one of these three signals, or else to the device HIBERNATE bit. The

signals are active high and each Regulator’s response to the selected signal is programmable as

defined in Table 84.

Note that, when a GPIO pin is configured as a Hibernate input pin, and this input is asserted, then all

LDO Regulators will be placed in Hibernate mode.

In order to use GPIO pins as L_PWR pins, they must be configured by setting the respective

GPn_FN, and GPn_DIR bits to the appropriate value (see Section 20).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Note: n

is a number between 1 and 4 that identifies the individual LDO regulator

R202 (CAh)

for LDO1

R205 (CDh)

for LDO2

R208 (D0h)

for LDO3

R211 (D3h)

for LDO4

13:12

LDOn_HIB_M

ODE [1:0]

LDO Hibernate behaviour:

00 = Select voltage image settings

01 = disable output

10 = reserved

11 = reserved

9:8

LDOn_HIB_T

RIG [1:0]

LDO Hibernate signal select

00 = Hibernate register bit

01 = L_PWR1

10 = L_PWR2

11 = L_PWR3

Table 84 Configuring Hardware Control for LDO Regulators

When the LDO Regulators are disabled, the output can be set to float or else the outputs can be

actively discharged through internal resistors. This feature is controlled using the register bits

described in Table 85.

Note that the “float” option is only supported when at least one other LDO Regulator remains enabled.

If LDO Regulators 1, 2, 3 and 4 are all disabled, then the LDO Regulator outputs will be discharged,

regardless of the LDOn_OPFLT registers.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R200 (C8h)

for LDO1

R203 (CBh)

for LDO2

R206 (CEh)

for LDO3

R209 (D1h)

for LDO4

LDOn_OPFLT

Enable discharge of LDOn outputs

when LDOn disabled

0 = Enabled - Output to be discharged

1 = Disabled - Output is left floating

Note - if LDO Regulators 1, 2, 3 and 4

are all disabled, then the outputs will all

be discharged, regardless of the

LDOn_OPFLT bit.

Note: n

is a number between 1 and 4 that identifies the individual LDO regulator

Table 85 Output Float Control for LDO Regulators

WM8351 Datasheet(PDF) 136 Page - Wolfson Microelectronics plc

WM8351 Datasheet(HTML) 136 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL