AD9915 datasheet(6/48 Pages) AD

6 / 48 page

AD9915

Data Sheet

Rev. A | Page 6 of 48

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

PARALLEL PORT TIMING

Write Timing

Address Setup Time to

WR Active

Address Hold Time to

WR Inactive

Data Setup Time to

WR Inactive

3.8

Data Hold Time to

WR Inactive

WR Minimum Low Time

2.1

WR Minimum High Time

3.8

Minimum

WR Time

10.5

Read Timing

Address to Data Valid

Address Hold to

RD Inactive

RD Active to Data Valid

RD Inactive to Data Tristate

RD Minimum Low Time

RD Minimum High Time

SERIAL PORT TIMING

SCLK Clock Rate (1/tCLK )

MHz

SCLK duty cycle = 50%

SCLK Pulse Width High, tHIGH

1.5

SCLK Pulse Width Low, tLOW

5.1

SDIO to SCLK Setup Time, tDS

4.9

SDIO to SCLK Hold Time, tDH

SCLK Falling Edge to Valid Data on

SDIO/SDO, tDV

CS to SCLK Setup Time, tS

CS to SCLK Hold Time, tH

CS Minimum Pulse Width High, tPWH

DATA PORT TIMING

D[31:0] Setup Time to SYNC_CLK

D[31:0] Hold Time to SYNC_CLK

F[3:0] Setup Time to SYNC_CLK

F[3:0] Hold Time to SYNC_CLK

IO_UPDATE Pin Setup Time to

SYNC_CLK

IO_UPDATE Pin Hold Time to

SYNC_CLK

Profile Pin Setup Time to SYNC_CLK

Profile Pin Hold Time to SYNC_CLK

DR_CTL/DR_HOLD Setup Time to

SYNC_CLK

DR_CTL/DR_HOLD Hold Time to

SYNC_CLK

DATA LATENCY (PIPELINE DELAY)

Single Tone Mode (Matched Latency

Disabled)

SYSCLK cycles = fS = system clock frequency

in GHz

Frequency

320

SYSCLK cycles

Phase

296

SYSCLK cycles

Amplitude

104

SYSCLK cycles

Single Tone Mode (Matched Latency

Enabled)

Frequency

320

SYSCLK cycles

Phase

320

Amplitude

320

SYSCLK cycles

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