AD9915 datasheet(33/48 Pages) AD

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Data Sheet

AD9915

Rev. A | Page 33 of 48

PARALLEL PROGRAMMING (8-/16-BIT)

The state of the external function pins (F0 to F3) determine the

type of interface used by the AD9915. Pin 28 to Pin 31 are

dedicated function pins. To enable the parallel mode interface

set Pin 28 to Pin 31 to logic low.

Parallel programming consists of eight address lines and either

eight or16 bidirectional data lines for read/write operations. The

logic state on Pin 22 determines the width of the data lines used. A

logic low on Pin 22 sets the data width to eight bits, and logic high

sets the data width to 16 bits. In addition, parallel mode has

dedicated write/read control inputs. If 16-bit mode is used, the

upper byte, Bits[15:8], goes to the addressed register and the

lower byte, Bits[7:0], goes to the adjacent lower address.

Parallel I/O operation allows write access to each byte of any

Table 12. Parallel Port Read Timing (See Figure 46)

Parameter

Value

Unit

Test Conditions/Comments

ADV

ns max

Address to data valid time

AHD

ns min

Address hold time to RD signal

inactive

RDLOV

ns max

RD low to output valid

RDHOZ

ns max

RD high to data three-state

RDLOW

ns max

RD signal minimum low time

RDHIGH

ns max

RD signal minimum high time

Table 13. Parallel Port Write Timing (See Figure 47)

Parameter

Value

Unit

Test Conditions / Comments

ASU

Address setup time to WR

signal active

DSU

3.8

Data setup time to WR signal

active

AHD

Address hold time to WR

signal inactive

DHD

Data hold time to WR signal

inactive

WRLOW

2.1

WR signal minimum low time

WRHIGH

3.8

WR signal minimum high time

10.5

Minimum write time

Figure 46. Parallel Port Read Timing Diagram

Figure 47. Parallel Port Write Timing Diagram

A[7:0]

D[7:0] OR

D[15:0]

tRDHOZ

tRDHIGH

tRDLOW

tRDLOV

tADV

tAHD

A[7:0]

D[7:0] OR

D[15:0]

tWR

tASU

tAHD

tWRHIGH

tDHD

tDSU

tWRLOW

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