AD1847 datasheet(20/28 Pages) AD

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AD1847

REV. B

–20–

IA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

Index

0000

LSS1

LSS0

res

LIG3

LIG2

LIG1

LIG0

0001

RSS1

RSS0

res

RIG3

RIG2

RIG1

RIG0

0010

LMX1

res

LX1G4

LX1G3

LX1G2

LX1G1

LX1G0

0011

RMX1

res

RX1G4

RX1G3

RX1G2

RX1G1

RX1G0

0100

LMX2

res

LX2G4

LX2G3

LX2G2

LX2G1

LX2G0

0101

RMX2

res

RX2G4

RX2G3

RX2G2

RX2G1

RX2G0

0110

LDM

res

LDA5

LDA4

LDA3

LDA2

LDA1

LDA0

0111

RDM

res

RDA5

RDA4

RDA3

RDA2

RDA1

RDA0

1000

res

FMT

C/L

S/M

CFS2

CFS1

CFS0

CSL

1001

res

ACAL

res

PEN

1010

XCTL1

XCTL0

CLKTS

res

1 0

1011

inval

1 1

1100

FRS

TSSEL

res

1 2

1101

DMA5

DMA4

DMA3

DMA2

DMA1

DMA0

res

DME

1 3

1110

inval

1 4

1111

inval

1 5

Figure 9. Register Map Summary

Control Register Mapping Summary

A detailed map of the control register bit assignments is summa-

rized for reference in Figure 9.

Daisy-Chained Multiple Codecs

Multiple AD1847s can be configured in a daisy-chain system

with a single master Codec and one or more slave Codecs.

Codecs in a daisy-chained configuration are synchronized at the

sample level.

The master and slave AD1847s should be powered-up together.

If this is not possible, the slave(s) should power-up before the

master Codec, such that the slave(s) are ready when the master

starts to drive the serial interface, and a serial data frame sync

(SDFS) can synchronize the master and slave(s).

The sample rate for the master and slave(s) should be pro-

grammed together. If this is not possible, the slave(s) should be

programmed before the master AD1847. A slave AD1847 enters

a time-out period after a new sample rate has been selected.

During this time-out period, a slave will ignore any activity on

the SDFS signal (i.e., frame syncs). There is no software means

to determine when a slave has exited from this time-out period

and is ready to respond to frame syncs. However, as long as the

AD1847 master is driving the serial interface, a frame sync will

not occur before the slave Codec(s) are ready.

Note that the time slots for all slave AD1847s must be assigned

to those slots which immediately follow the time slots consumed

by the master AD1847 so that the TSO (Time Slot Output)/TSI

(Time Slot Input) signaling operates properly. For example, in a

2-wire system with one master and one slave, the time slot as-

signment should be 0, 1, 2 (16, 17, 18) for the master AD1847,

and 3, 4, 5 (19, 20, 21) for the slave AD1847.

Figure 10 illustrates the connection between master and slave(s)

in a daisy-chained, multiple Codec system. Note that the TSI

pin of the master Codec should be tied to digital ground. The

XTAL1I pin of the slaves should be connected to digital

ground, and XTAL1O pin should be left unconnected, while

the XTAL2I pin should be connected to the CLKOUT pin of

the AD1847 master, and the XTAL2O pin generates a driven

version of the CLKOUT signal applied to the XTAL2I pin.

INITIALIZATION AND PROCEDURES

Reset and Power Down

A total reset of the AD1847 is defined as any event which

requires both the digital and analog section of the AD1847 to

return to a known and stable state. Total reset mode, as well as

power down, occurs when the PWRDOWN pin of the AD1847

has been asserted low for minimum power consumption. When

the PWRDOWN signal is deasserted, the AD1847 must be cali-

brated by setting the ACAL bit and exiting from the Mode

Change Enable (MCE) state.

The reset occurs, and only resets the digital section of the

AD1847, when the RESET pin of the AD1847 has been as-

serted LO to initialize all registers to known values. See the reg-

ister definitions for the exact values initialized. The register reset

defaults include TSSEL = 0 (1-wire system) and FRS = 0

(32 slots per frame). If the target application requires a 2-wire

system design or 16 slots per frame, the AD1847 can be

bootstrapped into these configurations.

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