AD1847 datasheet(21/28 Pages) AD

21 / 28 page

AD1847

REV. B

–21–

XTAL1I,O XTAL2I,O

TSO

CLKOUT

AD1847

(MASTER)

SCLK

SDFS

SDI

SDO

16.9344

MHz

24.576

MHz

TSI

XTAL2I

TSO

XTAL1I

(SLAVE 1)

SCLK

SDFS

SDI

SDO

XTAL1O

XTAL2O

N/C

TSI

XTAL2I

TSO

XTAL1I

(SLAVE 2)

SCLK

SDFS

SDI

SDO

XTAL1O

XTAL2O

N/C

Figure 10a. One-Wire Daisy-Chained Codec Interconnect

XTAL1I, O XTAL2I, O

TSO

CLKOUT

AD1847

(MASTER)

SCLK

SDFS

SDI

SDO

16.9344

MHz

24.576

MHz

TSI

XTAL2I

TSO

XTAL1I

(SLAVE 1)

SCLK

SDFS

SDI

SDO

XTAL1O

XTAL2O

N/C

TSI

XTAL2I

TSO

XTAL1I

(SLAVE 2)

SCLK

SDFS

SDI

SDO

XTAL1O

XTAL2O

N/C

Figure 10b. Two-Wire Daisy-Chained Codec Interconnect

To bootstrap into TSSEL = 1 (i.e., 2-wire system design), the

host CPU or DSP must transmit to the AD1847 in slot 0 a

Control Word with the MCE bit set HI, IA3:0 = “1100” to

address the Miscellaneous Information Index Register, and

DATA7:0 = “X100 000” to set the TSSEL bit HI. To bootstrap

into FRS = 1 (i.e., 16 slots per frame), the host CPU or DSP

must transmit to the AD1847 in slot 0 a Control Word with the

MCE bit set HI, IA3:0 = “1100” to address the Miscellaneous

Information Index Register, and DATA7:0 = “1X00 0000” to

set the FRS bit HI.

The host CPU or DSP must maintain the MCE bit set HI in

slot 16, which is the Control Word of the second sample of

the frame, so that the AD1847 does not initiate autocalibration

prematurely. At the next frame sync, the AD1847 will be

reconfigured.

The AD1847 must be reset after power up. When the RESET

signal is deasserted, the AD1847 will autocalibrate when the

MCE bit is reset LO (i.e., when exiting the Mode Change En-

able state) only if the ACAL bit is set. If the ACAL bit is not

set, the previous autocalibration values will be used.

The AD1847 will not function properly unless an auto-

calibration is performed after power up.

During power down, the serial port digital output pins and the

analog output pins take the following states:

SCLK–LO if BM is HI (i.e., bus master), input pin if BM is

LO (i.e., bus slave)

SDFS–LO if BM is HI, input pin if BM is LO

SDO–three-state

TSO–three-state

CLKOUT–LO if BM HI, three-state if BM is LO

VREF–pulled to analog ground

L_OUT, R_ OUT– pulled to analog ground

Clock Connections and Clock Rates

When the AD1847 is configured as a bus slave (BM = LO), the

XTAL1I pin should be connected to digital ground, and the

XTAL2I pin should be tied to the CLKOUT of the AD1847

bus master. The XTAL1O and the XTAL2O pins should be left

unconnected. When the AD1847 is configured as a bus master

(BM = HI), the XTAL1I and the XTAL1O pin should be con-

nected to a 24.576 MHz crystal, and the XTAL2I and

XTAL2O pin should be connected to a 16.9344 MHz crystal.

When XTAL1 is selected (by resetting the CSL bit LO in the

Data Format Register) as the clock source, the SCLK pin will

generated a serial clock at 12.288 MHz (or one half of the crys-

tal frequency applied at XTAL1), and the CLKOUT pin will

also generate a clock output at 12.288 MHz when the AD1847

is in bus master mode (BM = HI). When XTAL2 is selected (by

setting the CSL bit HI in the Data Format Register) as the clock

source, the SCLK pin will generate a serial clock at 11.2896 MHz

(or two thirds of the crystal frequency applied at XTAL2), and

the CLKOUT pin will generate a clock output at 16.9344 MHz

when the AD1847 is in bus master mode (BM = HI). The

CLKOUT pin will be three-stated when the AD1847 is placed

in bus slave mode (BM = LO).

When the selected frame size is 32 slots per frame (by resetting

the FRS bit LO in the Miscellaneous Information Register), the

SDFS pin will generate a serial data frame sync at the frequency

of the selected sample rate divided by two, when the AD1847 is

in bus master mode (BM = HI). When the selected frame size is

16 slots per frame (by setting the FRS bit HI in the Miscella-

neous Information Register), the SDFS pin will generate a serial

data frame sync at the frequency of the selected sample rate,

when the AD1847 is in bus master mode (BM = HI).

AD1847 Datasheet(PDF) 21 Page - Analog Devices

AD1847 Datasheet(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL