ADMC300

–40–

REV. B

ADC BANK A

PWMSYNC

ADC BANK B

EVENT TIMER

DM (0x201D)

PICMASK (R/W)

PWMTRIP

0 = DISABLE

(MASK)

1 = ENABLE

ENCODER INTERFACE

0

0

0

0

0

0

0

00

0

0

00

0

0

0

PIO3

PIO2

PIO1

PIO0

PIO (PIO4 TO PIO11)

0 = DISABLE

(MASK)

1 = ENABLE

IMASK (R/W)

PERIPHERAL (OR

IRQ2)

RESERVED (SET TO 0)

SPORT0 TRANSMIT

SPORT0 RECEIVE

TIMER

SPORT1 RECEIVE

(OR

IRQ0)

SPORT1 TRANSMIT

(OR

IRQ1)

SOFTWARE 0

SOFTWARE 1

0 = DISABLE

(MASK)

1 = ENABLE

0

0

0

0

0

0

0

00

0

0

00

1

1

0

DSP REGISTER

0 = DISABLE

(MASK)

1 = ENABLE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

1

0

0

0

IRQ0 SENSITIVITY

0 = LEVEL

1 = EDGE

ICNTL

IRQ1 SENSITIVITY

IRQ2 SENSITIVITY

INTERRUPT NESTING

0 = DISABLE

1 = ENABLE

DSP REGISTER

SPORT1 RECEIVE OR

IRQ0

INTERRUPT FORCE

INTERRUPT CLEAR

TIMER

SOFTWARE 0

SOFTWARE 1

SPORT0 RECEIVE

SPORT0 TRANSMIT

IRQ2

SPORT1 RECEIVE OR

IRQ0

TIMER

SOFTWARE 0

SOFTWARE 1

SPORT0 RECEIVE

SPORT0 TRANSMIT

SPORT1 TRANSMIT OR

IRQ1

IRQ2

SPORT1 TRANSMIT OR

IRQ1

IFC

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DSP REGISTER

43

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Figure 27. Configuration of ADMC300 Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset for R/W registers. Reserved bits are shown on a

gray field – these bits should always be written as shown.