ADMC300 datasheet(3/42 Pages) AD

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–3–

REV. B

ADMC300

VOLTAGE REFERENCE

Parameter

Test Conditions

Min

Typ

Max

Unit

VREF

Voltage Level

2.25

2.75

Source Current

–100

µA

Power Supply Rejection Ratio (PSRR)

–5

mV/V

Specifications subject to change without notice.

PULSEWIDTH MODULATOR

Parameter

Test Conditions

Min

Typ

Max

Unit

Counter Resolution1

Bits

Edge Resolution

Double Update Mode

Programmable Dead Time

81.84

µs

Programmable Dead Time Increments

TMIN

Programmable Pulse Deletion

40.92

µs

Programmable Deletion Increments

fPWM

PWM Frequency Range1

191

TSYNC

PWMSYNC Pulsewidth

0.04

10.24

µs

fCHOP

Gate Drive Chop Frequency

0.0244

6.25

MHz

NOTES

1Resolution varies with PWM switching frequency, 191 Hz = 16 bits, 3.05 kHz = 12 bits, 48.8 kHz = 8 bits (12.5 MHz CLKIN) in single update mode.

Specifications subject to change without notice.

(VDD = AVDD = 5 V

10%, GND = AGND = 0 V, VREFIN = 2.50 V, TAMB = –40 C to +85 C,

CLKIN = 12.5 MHz, unless otherwise noted)

(VDD = AVDD = 5 V

10%, GND = AGND = 0 V, TAMB = –40 C to +85 C, CLKIN = 12.5 MHz, unless

otherwise noted)

(VDD = AVDD = 5 V

10%, GND = AGND = 0 V, TAMB = –40 C to +85 C, CLKIN = 12.5 MHz, unless otherwise

noted)

ANALOG-TO-DIGITAL CONVERTER

Parameter

Test Conditions

Min

Typ

Max

Unit

Signal-to-Noise Ratio

1 (SNR)

@VDD = 5.0 V,

Total Harmonic Distortion

1 (THD)

@ fS = 32.55 kHz,

–70

Common-Mode Rejection Ratio

2 (CMRR)

@ fIN = 1.017 kHz,

–82

Channel-Channel Crosstalk

ADCDIVn = 0x180,

–76

Gain Error

V1–V5 = 4.0 V p-p

Gain

V1N–V5N = VREFIN = 2.5 V

10,600

LSB/V

VIN

Analog Input Range

0VDD

VDIFF

Analog Input Voltage (Differential)

VDD/2

VOFFSET

DC Offset Voltage

fMOD, MAX

Maximum Sigma-Delta Modulator Rate

ADCDIVA = 0x180

2.08

MHz

ADCDIVB = 0x180

fS, MAX

Maximum ADC Sample Rate

ADCDIVA = 0x180

32.55

kHz

ADCDIVB = 0x180

VREFIN

Reference Input Voltage

2.4

2.5

2.6

RIN

Equivalent Input Resistance

Ω

NOTES

1SNR measured with ADC channel configured in single-ended mode. SNR measurement does not include harmonic distortion, THD includes first six harmonics.

The effective number of bits (ENOB) is related to the SNR by SNR = 6.02 (ENOB) +1.76 dB. Input signal filtered at 1.5 kHz.

2Input signal applied to both pins of input differential pair of ADC channel.

3Input signal applied to four ADC channels, dc applied to fifth, measurement taken at fifth ADC channel.

4Peak-peak input voltage in differential input configuration is half that in single-ended mode.

5This offset may be corrected for, using the ADC calibration feature.

6At maximum sigma-delta modulator rate of 2.08 MHz.

7Input reference pins: REFINA, REFINB.

8Analog signal input pins: V1–V5, V1N–V5N.

Specifications subject to change without notice.

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