ADMC300 datasheet(14/42 Pages) AD

14 / 42 page

ADMC300

–14–

REV. B

The corresponding configuration for single-ended operation is

shown in Figure 7, where the inverting input is now tied directly to

the reference voltage level. The noninverting input is VIN + VREF.

An antialiasing filter with a cutoff at 34 kHz is included on this

input. Clearly, the differential input voltage swing in this con-

figuration is half that of the differential configuration. There-

fore, when operating in single-ended mode, the input voltage,

VIN, may be twice as large as that when operating differentially.

To ensure correct operation, a 0.1

µF, high-quality capacitor

must be included at the reference input pins. A 0.1

µF capaci-

tor should also be used at the VREF pin, even if external refer-

ences are used.

In both Figures 6 and 7, it is assumed that an external precision

reference is used to provide the reference voltage level, VREF.

For optimum operation, a high-performance 2.5 V reference

such as the AD580 is recommended. This reference is applied

directly to both input reference pins, REFINA and REFINB,

and is also applied to any external bias circuitry used to produce

the ADC input signals. For a lower cost solution, the ADMC300

also provides a reference output that may be used to provide the

VREF signal. The reference output is available at the VREF pin.

For correct operation, a 0.1

µF capacitor is required at this pin

even if the internal reference is not used. In addition, it is rec-

ommended that the VREF signal be buffered in a unity-gain stage

prior to use, as shown in Figure 8. Of course, since there are

two separate reference inputs, pins REFINA and REFINB, the

two banks of ADCs may be run differently, if required.

ADC Register Update

The sigma-delta converters of the ADMC300 operate at a

highly oversampled rate. A number of control bits in the

ADCCTRL register are used to control when and how data is

latched into the ADC data registers of each bank. The data

registers of each bank may be latched at a regular rate based on

either an internal or an external convert start signal. Bits 0–1 of

the ADCCTRL register determine whether the convert start

signal is internal or external. Bit 0 controls the operation of

Bank A and Bit 1 controls the operation of Bank B. If either of

these bits is set to 1, the data registers of the corresponding

ADC bank are latched within two CLKIN cycles of the occur-

rence of a rising edge on the CONVST pin (PIO9). Alterna-

tively, if either bit is set to zero, internal mode is selected and

the ADCs of the particular bank are updated at a regular rate,

determined by the contents of the appropriate ADC sample

frequency division register, ADCDIVA or ADCDIVB.

Bits 2–3 of the ADCCTRL register can be used to place the

ADC banks in an alternative read mode. The read mode is

enabled by setting these bits to 1, effectively disabling the con-

vert start mode. In the read mode, the ADC registers of the

particular bank are continuously updated at a rate equal to half

the DSP clock rate, so that data is effectively available on de-

mand. Bit 2 of the ADCCTRL register is used to place ADC

Bank A in read mode, while Bit 3 is used for Bank B.

ADC Sample Rate Selection

Internal convert start mode is selected by clearing Bits 0 and 2

of the ADCCTRL register for Bank A and Bits 1 and 3 for Bank

B. In this mode, the ADC data registers are updated at a regu-

lar rate that is determined by the ADC clock divide registers,

ADCDIVA and ADCDIVB. Therefore, each bank can be con-

figured for independent update rates by writing different values

to the two registers. When Bank A and Bank B are configured

for independent update rates, it is important that the REFINA

and REFINB pins are driven by separate voltage reference sources

to avoid excessive crosstalk between banks. The ADCDIVA and

ADCDIVB registers are 6-bit registers aligned in Bits 6–11 and

the value written to these registers is used to divide the CLKIN

frequency to provide the ADC update rate. A 12-bit value is

written to these registers, but since Bits 0–5 are ignored, the

value should be an integer multiple of 64 or 0x040. The result-

ant ADC update rates for Banks A and B may be expressed as:

f S, A

f CLKIN

ADCDIVA

f S, B

f CLKIN

ADCDIVB

where fCLKIN is the CLKIN frequency, equal to half the DSP

instruction rate. Therefore, writing a value of 0x180 (= 384)

gives an ADC update rate of 32.55 kHz with a CLKIN frequency

of 12.5 MHz. The maximum value that can be written to these

registers is 0xFC0, corresponding to an update rate of 3.1 kHz.

Since the maximum update rate is limited to 32.55 kHz, the per-

missible range of ADC divide values is 0x180 to 0xFC0 in steps

of 0x040.

Each ADC channel contains an input modulator that oversamples

the input signal at a high rate. The modulator sample frequency

is automatically set by the internal ADC control to be exactly

64 times the ADC update rate determined by the ADC divide

registers. This corresponds to an oversample ratio of 64. There-

fore, in the case where ADCDIVA = 0x180, the input modulators

of ADC Bank A sample the input signal at 2.08 MHz and the

data registers ADC1 and ADC2 are updated at the 32.55 kHz

rate.

Synchronization of ADC and PWM Systems

In motor control applications, it is advantageous to synchronize

the operation of the ADC system to the PWM pulse generation.

The ADMC300 permits separate control of such synchroniza-

tion for each ADC bank and permits sophisticated definition of

the particular way that the ADC and PWM systems are synchro-

nized. Operation of Bank A of the ADC may be synchronized to

the PWM by setting Bit 7 of the ADCCTRL register. Similarly,

setting Bit 8 of the ADCCTRL register enables synchronization

of Bank B to the PWM.

At its simplest, the ADC and PWM systems may be programmed

to operate at the same frequency and be synchronized to one

another so that the ADC data registers are automatically updated

at the start of each PWM period. This mode of operation is

illustrated in Figure 9(a) and is enabled by writing identical

values to the PWM period register, PWMTM, and the ADC

divide register, ADCDIVA or ADCDIVB. Synchronization is

subsequently enabled by setting Bit 7 (for Bank A) or Bit 8 (for

Bank B) of the ADCCTRL register.

Additionally, a separate control register, ADCSYNC may be

used to phase shift the update of the ADC registers to some

suitably defined instant within the PWM period. In this mode,

the frequencies of the PWM and ADC register updating are still

the same but phase shifted relative to one another. This mode is

illustrated in Figure 9 (b). Again, the PWM period register and

ADC divide registers are loaded with the same value. However,

the offset of the ADC update within the PWM period is

programmed using the ADCSYNC register. The ADCSYNC

ADMC300 Datasheet(PDF) 14 Page - Analog Devices

ADMC300 Datasheet(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Datasheet Download

Link URL