ADMC300 datasheet(29/42 Pages) AD

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ADMC300

–29–

REV. B

Interrupt Configuration

The IFC and ICNTL registers of the DSP core control and

configure the interrupt controller of the DSP core. The IFC

any of the eight DSP interrupts. Bits 0 to 7 of the IFC register

may be used to clear the DSP interrupts while Bits 8 to 15 can be

used to force a corresponding interrupt. Writing to Bits 11 and 12

in IFC is the only way to create the two software interrupts.

The ICNTL register is used to configure the sensitivity (edge or

level) of the

IRQ0, IRQ1 and IRQ2 interrupts and to enable/

disable interrupt nesting. Setting Bit 0 of ICNTL configures the

IRQ0 as edge sensitive while clearing the bit configures it for

level sensitive. Bit 1 is used to configure the

IRQ1 interrupt and

Bit 2 is used to configure the

IRQ2 interrupt. It is recommended

that the

IRQ2 interrupt be always configured for level sensitive

as this ensures that no peripheral interrupts are lost. Setting Bit 4

of the ICNTL register enables interrupt nesting. The configura-

tion of both IFC and ICNTL registers is shown at the end of

the data sheet.

Interrupt Operation

Following a reset, the ROM code monitor of the ADMC300

copies a default interrupt vector table into program memory

RAM from address 0x0000 to 0x005F. Since each interrupt

source has a dedicated four word space in this vector table, it is

possible to code short interrupt service routines (ISR) in place.

Alternatively, it may be required to insert a JUMP instruction to

the appropriate start address of the interrupt service routine if

more memory is required for the ISR.

On the occurrence of an interrupt, the program sequencer en-

sures that there is no latency (beyond synchronization delay)

when processing unmasked interrupts. In the case of the timer,

SPORT0, SPORT1 and software interrupts, the interrupt con-

troller automatically jumps to the appropriate location in the

interrupt vector table. At this point, a JUMP instruction to the

appropriate ISR is required.

In the event of a motor control peripheral interrupt, the opera-

tion is slightly different. For any of the eleven peripheral inter-

rupts, the interrupt controller automatically jumps to location

0x0004 in the interrupt vector table. In addition, the required

vector address (between 0x0030 and 0x0058) associated with

the particular interrupt source is placed in the PICVECTOR

the monitor on reset subsequently performs a JUMP from loca-

tion 0x0004 to the address specified in the PICVECTOR regis-

ter. This operation with the PICVECTOR register results in a

slightly longer latency associated with processing any of the

peripheral interrupts, as compared with the latency of the inter-

nal DSP core interrupts.

The code located at location 0x0004 by the monitor on reset is

as follows:

0x0004: DM (I4_SAVE) = I4;

I4 = DM (PICVECTOR);

JUMP (I4

);

The default code for each of the motor control peripherals is:

I4 = DM (I4_SAVE);

RTI;

Note that this default restores I4 to its value before the inter-

rupt. The user should replace the RTI with a JUMP to their

ISR. The PUT_VECTOR ROM subroutine can be used to

replace the RTI with the JUMP.

The PIC block manages the sequencing of the eleven motor

control peripheral interrupts. In the case of multiple simulta-

neous interrupts, the PIC will load the PICVECTOR register

with the vector address of the highest priority pending interrupt.

The contents of the PICVECTOR register will remain fixed

until read by the DSP. This action is performed by the default

DSP code at location 0x0004. The PIC block only asserts a

new interrupt after the PICVECTOR register has been read.

SYSTEM CONTROLLER

The system controller block of the ADMC300 performs a num-

ber of distinct functions:

1. Manages the interface and data transfer between the DSP

core and the motor control peripherals.

2. Controls the multiplexing of the SPORT1 pins to select

either the DR1A or DR1B data receive pins. It also allows

configuration of SPORT1 as a UART interface.

3. Manages the software flags of the DSP core.

4. Contains a status register (SYSSTAT) that indicates the

state of the

PWMTRIP, PWMPOL pins and the watchdog

timer.

5. Performs a reset of the motor control peripherals and control

registers following a hardware, software or watchdog initiated

reset.

DSP

CORE

SPORT1

DR1A

DR1B

TFS1

RFS1/

SROM

SCLK1

MODECTRL (5…4)

UARTEN

DR1SEL

DT1

DR1

TFS1

RFS1

SCLK1

FL1

ADMC300

DT1

Figure 19. Internal Multiplexing of SPORT1 Pins

SPORT1 Control

The ADMC300 uses SPORT1 as the default serial port for boot

loading and as the interface to the development environment.

There are two data receive pins, DR1A and DR1B, on the

ADMC300. This permits DR1A to be used as the data receive

pin when interfacing to serial ROM or E

2PROM for boot load-

ing. Alternatively, if connecting through another external device

for either boot loading or interface to the development environ-

ment, the DR1B pin can be used. Both data receive pins are

multiplexed internally into the single data receive input of

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