ADMC300 datasheet(19/42 Pages) AD

19 / 42 page

ADMC300

–19–

REV. B

In single update mode, a single PWMSYNC pulse is produced

in each PWM period. The rising edge of this signal marks the

start of a new PWM cycle and is used to latch new values from

the PWM configuration registers (PWMTM, PWMDT, PWMPD

and PWMSYNCWT) and the PWM duty cycle registers

(PWMCHA, PWMCHB and PWMCHC) into the three-phase

timing unit. In addition, the PWMSEG register is also latched

into the output control unit on the rising edge of the PWM-

SYNC pulse. In effect, this means that the characteristics and

resultant duty cycles of the PWM signals can be updated only

once per PWM period at the start of each cycle. The result is

that PWM patterns that are symmetrical about the midpoint of

the switching period are produced.

In double update mode, there is an additional PWMSYNC

pulse produced at the midpoint of each PWM period. The

rising edge of this new PWMSYNC pulse is again used to latch

new values of the PWM configuration registers, duty cycle

registers and the PWMSEG register. As a result it is possible to

alter both the characteristics (switching frequency, dead time,

minimum pulsewidth and PWMSYNC pulsewidth) as well as

the output duty cycles at the midpoint of each PWM cycle.

Consequently, it is possible to produce PWM switching patterns

that are no longer symmetrical about the midpoint of the period

(asymmetrical PWM patterns).

In double update mode, it may be necessary to know whether

operation at any point in time is in either the first half or the

second half of the PWM cycle. This information is provided by

Bit 3 of the SYSSTAT register, which is cleared during opera-

tion in the first half of each PWM period (between the rising

edge of the original PWMSYNC pulse and the rising edge of

the new PWMSYNC pulse introduced in double update mode).

Bit 3 of the SYSSTAT register is set during operation in the

second half of each PWM period. This status bit allows the user

to make a determination of the particular half-cycle during

implementation of the PWMSYNC interrupt service routine, if

required.

The advantage of double update mode is that lower harmonic

voltages can be produced by the PWM process and faster con-

trol bandwidths are possible. However, for a given PWM switching

frequency, the PWMSYNC pulses occur at twice the rate in the

double update mode. Since new duty cycle values must be

computed in each PWMSYNC interrupt service routine, there

is a larger computational burden on the DSP in double update

mode.

Width of the PWMSYNC Pulse, PWMSYNCWT Register

The PWM controller of the ADMC300 produces an output

PWM synchronization pulse at a rate equal to the PWM switch-

ing frequency in single update mode and at twice the PWM

frequency in the double update mode. This pulse is available

for external use at the PWMSYNC pin. The width of this

PWMSYNC pulse is programmable by the 8-bit read/write

PWMSYNCWT register. The width of the PWMSYNC pulse,

TPWMSYNC, is given by:

TPWMSYNC = tCK

× (PWMSYNCWT + 1)

so that the width of the pulse is programmable from tCK to

256tCK (corresponding to 40 ns to 10.24

µs for a CLKOUT rate

of 25 MHz). Following a reset, the PWMSYNCWT register

contains 0x27 (= 39) so that the default PWMSYNC width is

1.6

µs.

PWM Duty Cycles, PWMCHA, PWMCHB, PWMCHC

Registers

The duty cycles of the six PWM output signals on pins AH to

CL are controlled by the three 16-bit read/write duty cycle

registers, PWMCHA, PWMCHB and PWMCHC. The integer

value in the register PWMCHA controls the duty cycle of the

signals on AH and AL, PWMCHB controls the duty cycle of

the signals on BH and BL and PWMCHC controls the duty

cycle of the signals on CH and CL. The duty cycle registers are

programmed in integer counts of the fundamental time unit,

tCK, and define the desired on-time of the high-side PWM sig-

nal produced by the three-phase timing unit over half the PWM

period. The switching signals produced by the three-phase

timing unit are also adjusted to incorporate the programmed

dead time value in the PWMDT register. The three-phase timing

unit produces active LO signals so that a LO level corresponds to a

command to turn on the associated power device.

A typical pair of PWM outputs (in this case for AH and AL)

from the timing unit are shown in Figure 12 for operation in

single update mode. All illustrated time values indicate the

integer value in the associated register and can be converted to

time by simply multiplying by the fundamental time increment,

tCK. First, it is noted that the switching patterns are perfectly

symmetrical about the midpoint of the switching period in this

single update mode since the same values of PWMCHA,

PWMTM and PWMDT are used to define the signals in both

half cycles of the period. It can be seen how the programmed

duty cycles are adjusted to incorporate the desired dead time

into the resultant pair of PWM signals. Clearly, the dead time is

incorporated by moving the switching instants of both PWM

signals (AH and AL) away from the instant set by the PWMCHA

(PWMDT

× t

CK) to preserve the symmetrical output patterns.

Also shown is the PWMSYNC pulse whose width is set by the

PWMSYNCWT register and Bit 3 of the SYSSTAT register

that indicates whether operation is in the first or second half

cycle of the PWM period.

PWMSYNC

PWMCHA

PWMDT

PWMSYNCWT + 1

PWMDT

SYSSTAT (3)

PWMTM

Figure 12. Typical PWM Outputs of Three-Phase Timing

Unit in Single Update Mode (Active LO Waveforms)

The resultant on-times of the PWM signals in Figure 12 may be

written as:

TAH = 2

× (PWMCHA – PWMDT) × t

TAL = 2

× (PWMTM – PWMCHA – PWMDT) × t

and the corresponding duty cycles are:

dAH

T AH

PWMCHA – PWMDT

PWMTM

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