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ADMC300

–20–

REV. B

dAL

T AL

PWMTM – PWMCHA – PWMDT

PWMTM

The minimum permissible TAH and TAL values are zero, corre-

sponding to a 0% duty cycle. In a similar fashion, the maximum

value is TS, corresponding to a 100% duty cycle.

The output signals from the timing unit for operation in double

update mode are shown in Figure 13. This illustrates a com-

pletely general case where the switching frequency, dead time

and duty cycle are all changed in the second half of the PWM

period. Of course, the same value for any or all of these quanti-

ties could be used in both halves of the PWM cycle. However, it

can be seen that there is no guarantee that symmetrical PWM

signals will be produced by the timing unit in double update

mode. Additionally, it is seen that the dead time is inserted into

the PWM signals in the same way as in the single update mode.

PWMCHA2

PWMDT1

PWMDT2

PWMSYNCWT2 + 1

PWMCHA1

PWMTM1

PWMTM2

PWMSYNCWT1 + 1

PWMSYNC

SYSSTAT (3)

Figure 13. Typical PWM Outputs of Three-Phase Timing

Unit in Double Update Mode (Active LO Waveforms)

In general the on-times of the PWM signals in double update

mode can be defined as:

T AH

= (PWMCHA

+ PWMCHA

2 – PWMDT 1 – PWMDT 2 )

× t

T AL

= (PWMTM

+ PWMTM

2 – PWMCHA1 – PWMCHA

– PWMDT1 – PWMDT 2 )

× t

where the subscript 1 refers to the value of that register during

the first half cycle and the subscript 2 refers to the value during

the second half cycle. The corresponding duty cycles are:

PWMCHA

PWMDT

PWMTM

(

––

)

()

PWMTM

PWMCHA

PWMDT

PWMTM

(

––

–

)

()

since for the completely general case in double update mode, the

switching period is given by:

= (PWMTM

+ PWMTM

2 )

× t

Again, the values of TAH and TAL are constrained to lie between

zero and TS.

PWM signals similar to those illustrated in Figure 12 and Figure

13 can be produced on the BH, BL, CH and CL outputs by

programming the PWMCHB and PWMCHC registers in a

manner identical to that described for PWMCHA.

The PWM controller does not produce any PWM outputs until

all of the PWMTM, PWMCHA, PWMCHB and PWMCHC

registers have been written to at least once. Once these registers

have been written, internal counting of the timers in the

three-phase timing unit is enabled. Writing to the PWMTM

vided the PWMTM register is written prior to the PWMCHA,

PWMCHB and PWMCHC registers in the initialization,

the first PWMSYNC pulse and interrupt (if enabled) appear

1.5

× t

× PWMTM seconds after the initial write to the

PWMTM register in single update mode. In double update

mode, the first PWMSYNC pulse appears after PWMTM

tCK seconds.

Effective PWM Resolution

In single update mode, the same value of PWMCHA, PWMCHB

and PWMCHC is used to define the on-times in both half

cycles of the PWM period. As a result the effective resolution

of the PWM generation process is 2tCK (or 80 ns for a 25 MHz

CLKOUT), since incrementing one of the duty cycle registers

by one changes the resultant on-time of the associated PWM

signals by tCK in each half period (or 2tCK for the full period).

In double update mode, improved resolution is possible since

different values of the duty cycle registers are used to define the

on-times in both the first and second halves of the PWM pe-

riod. As a result, it is possible to adjust the on-time over the

whole period in increments of tCK. This corresponds to an

effective PWM resolution of tCK in double update mode (or

40 ns for a 25 MHz CLKOUT).

The achievable PWM switching frequency at a given PWM

resolution is tabulated in Table V.

Table V. Achievable PWM Resolution in Single and Double

Update Modes

Single Update Mode

Double Update Mode

Resolution

PWM Frequency

(Bits)

(kHz)

48.8

97.6

24.4

48.8

12.2

24.4

6.1

12.2

3.05

6.1

Minimum Pulsewidth, PWMPD Register

In many power converter switching applications, it is desirable

to eliminate PWM switching signals below a certain width. It

takes a certain finite time to both turn on and turn off modern

power semiconductor devices. Therefore, if the width of any of

the PWM signals goes below some minimum value, it may be

desirable to completely eliminate the PWM switching for that

particular cycle.

The allowable minimum on-time for any of the six PWM out-

puts over half a PWM period that can be produced by the

PWM controller may be programmed using the PWMPD regis-

ter. The minimum on-time is programmed in increments of tCK

so that the minimum on-time that will be produced over any

half PWM period, TMIN, is related to the value in the PWMPD

TMIN = PWMPD

× tCK

so that a PWMPD value of 0x002 defines a permissible mini-

mum on-time of 80 ns for a 25 MHz CLKOUT.

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