ADMC300

–34–

REV. B

0

0

0

0

0

0

0

0

0

0

0

00

0

0

0

ADCCAL (R/W)

DM (0x203B)

ADC1 CALIBRATION

ADC2 CALIBRATION

ADC3 CALIBRATION

ADC4 CALIBRATION

ADC5 CALIBRATION

0 = DISABLE

1 = ENABLE

DM (0x2039)

ADC BANK A DIVIDE VALUE

ADCDIVA (R/W)

0

0

1

1

0

0

0

01

1

1

10

0

0

0

DM (0x203A)

ADC BANK B DIVIDE VALUE

ADCDIVB (R/W)

0

0

1

1

0

0

0

01

1

1

10

0

0

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Figure 21. Configuration of ADMC300 Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset for R/W registers. Reserved bits are shown on a

gray field – these bits should always be written as shown.