ADMC300 datasheet(23/42 Pages) AD

23 / 42 page

ADMC300

–23–

REV. B

EIUMAXCNT. There is also a single north marker mode avail-

able in which the encoder quadrature counter is reset only on

the first zero pulse. Both modes are enabled by dedicated con-

trol bits in the EIU control register, EIUCTRL. A status bit is

set in the EIUSTAT register on the first occurrence of the zero

pulse.

The Encoder Interface Unit can also be made to implement

some error checking functions. If the error checking mode is

enabled, upon the occurrence of a zero pulse, the contents of

the encoder counter register are compared with the expected

value (0 or EIUMAXCNT depending on the direction of rota-

tion). If an encoder count error is detected (say due to a discon-

nected encoder line), a status bit in the EIUSTAT register is set

and an EIU interrupt is generated.

An additional status bit is provided in the EIUSTAT register,

which indicates the initialization state of the EIU. Until the

EIUMAXCNT register is written to, the EIU is not initialized.

Three status bits in the EIUSTAT register can also be read to

read the state of the three EIU pins, EIA, EIB and EIZP.

The Encoder Interface Unit of the ADMC300 contains a 16-bit

loop timer that behaves in a manner similar to the program-

mable interval timer of the DSP core. The loop timer consist of

a timer register, period register and scale register so that it can

be programmed to time-out and reload at appropriate intervals.

A control bit in the EIUCTRL register is used to enable/disable

this loop timer. When this loop timer times out, an EIU inter-

rupt is generated. This interrupt could be used to control the

timing of speed and position control loops in high performance

drives.

The Encoder Interface Unit also includes a high performance

Encoder Event Timer (EET) block that permits the accurate

timing of successive events of the encoder inputs. The EET can

be programmed to time the duration between up to 256 encoder

pulses and can be used to enhance velocity estimation, particu-

larly at low speeds of rotation. The information from the regis-

ters of the EET block can be latched in two ways. In one mode,

both the contents of the EIU quadrature count register, EIUCNT

and all relevant EET registers (EETT and EETDELTAT) are

latched when the EIU loop timer times out. In the second

mode, the act of reading the EIUCNT register also simulta-

neously latches the EET registers. The EET data latching mode

is selected by a control bit in the EIUCTRL register.

Encoder Loop Timer

The EIU contains a 16-bit loop timer that is structured in a

manner similar to the interval timer of the DSP core (TCOUNT,

TPERIOD and TSCALE registers). The corresponding regis-

ters of the encoder loop timer are EIUTIMER, EIUPERIOD

and EIUSCALE. The EIU loop timer is clocked at the CLKIN

rate.

The EIU loop timer can be used to generate periodic interrupts

based on multiples of the CLKIN cycle times. The EIU loop

timer is enabled by setting Bit 5 of the EIUCTRL register.

When enabled, the 16-bit timer register (EIUTIMER) is decre-

mented every N cycles, where N-1 is the scaling value stored in

the 8-bit EIUSCALE register. When the value of the EIUTIMER

EIUTIMER register is reloaded with the 16-bit value in the

EIUPERIOD register.

The scaling feature of this timer, provided by the EIUSCALE

over a wide range of periods. For a 12.5 MHz CLKIN rate

(80 ns period), the timer can generate interrupts with periods of

80 ns up to 5.24 ms with a zero scale value (EIUSCALE = 0).

When scaling is used, time periods can range up to 1.34 seconds.

The EIU interrupt can be masked in the PICMASK register.

Encoder Interface Structure and Operation

The functional block diagram of the entire encoder interface

system of the ADMC300 is shown in Figure 16. The encoder

interface section consists of a 16-bit quadrature up/down counter,

a 16-bit read/write EIUCNT register that allows the up/down

counter to be read by the DSP. There is also a 16-bit read/

write EIUMAXCNT register that must be written to initialize

the encoder system. Until the EIUMAXCNT register has been

written to, the Encoder Interface Unit is not initialized and Bit 2

of the EIUSTAT register is set. The contents of the EIUMAXCNT

ture counter. The contents of the EIUMAXCNT register are

also used for error checking of the EIU. Operation of the en-

coder interface is controlled by the 6-bit read/write EIUCTRL

Typical encoder waveforms are illustrated in Figure 17. The

contents of the quadrature counter are updated on each edge of

both encoder signals applied on the EIA and EIB pins. Prior to

application to the quadrature counter, these signals are synchro-

nized to the CLKIN rate in input synchronization buffers. This

eliminates the asynchronous nature of real world encoder signals

prior to use in the Encoder Interface Unit logic.

Encoder Counter Direction

The direction of quadrature counting is determined by the REV

bit (Bit 0) of the EIUCTRL register. If the REV bit is cleared,

the signal at the EIA pin is fed to the A input of the quadrature

counter, and the EIB pin is fed to the B input. Thus, if the EIA-

encoder signal leads the EIB signal (and therefore the A signal

leads the B signal), the quadrature counter is incremented on

each edge, as shown in Figure 17. This (A signal leads the B

signal) is defined as the forward direction of motion. Setting

Bit 0 of the EIUCTRL register causes the signal at the EIA pin

to be fed to the B input of the quadrature counter and the signal

EIB becomes the A input of the quadrature counter. Therefore,

if the EIA signal leads the EIB signal at the pins of the ADMC300,

the A input to the quadrature counter will now lag the B input.

This will be recognized as rotation in the reverse direction and

the counter will be decremented on each quadrature pulse.

Following a reset, the REV bit is cleared.

As shown in Figure 16, the two encoder signals are used to

derive a quadrature signal that is used, in conjunction with a

direction bit, to increment or decrement the encoder counter

and also the Encoder Event Timer. The status of the direction

signal is indicated at Bit 1 of the EIUSTAT register. While the

encoder counter is incrementing, Bit 1 is set. Alternatively,

when the encoder counter is decrementing, Bit 1 of the EIUSTAT

ADMC300 Datasheet(PDF) 23 Page - Analog Devices

ADMC300 Datasheet(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Datasheet Download

Link URL