ADMC300 datasheet(18/42 Pages) AD

18 / 42 page

ADMC300

–18–

REV. B

The PWM controller is driven by a clock at the same frequency

as the DSP instruction rate, CLKOUT, and is capable of gener-

ating two interrupts to the DSP core. One interrupt is generated

on the occurrence of a PWMSYNC pulse and the other is gen-

erated on the occurrence of any PWM shutdown action.

PWMCHA (15…0)

PWMCHB (15…0)

PWMCHC (15…0)

PWMSEG

(8…0)

PWMGATE

(8…0)

THREE-PHASE

PWM TIMING

UNIT

OUTPUT

CONTROL

UNIT

CLK

SYNC

RESET

SYNC

PIO

PWM

DETECT

GATE

DRIVE

UNIT

CLK

POL

CLKOUT

PWMTM (15…0)

PWMDT (9…0)

PWMPD(9…0)

PWMSYNCWT(7…0)

MODECTRL (6)

PWMSWT

(0)

PIOPWM

(11…0)

PWMTRIP

PWMSYNC

PWMPOL

PIO0

PIO11

TO INTERRUPT

CONTROLLER

PWM

CONFIGURATION

REGISTERS

PWM

DUTY CYCLE

REGISTERS

PWMSYNC

PWMTRIP

PWM SHUTDOWN CONTROLLER

Figure 11. PWM Controller Overview

Three-Phase Timing Unit

The 16-bit three-phase timing unit is the core of the PWM

controller and produces three pairs of pulsewidth modulated

signals with high resolution and minimal processor overhead.

The outputs of this timing unit are active LO such that a low

level is interpreted as a command to turn ON the associated

power device. There are four main configuration registers

(PWMTM, PWMDT, PWMPD and PWMSYNCWT) that

determine the fundamental characteristics of the PWM outputs.

In addition, the operating mode of the PWM (single or double

update mode) is selected by Bit 6 of the MODECTRL register.

These registers, in conjunction with the three 16-bit duty cycle

registers (PWMCHA, PWMCHB and PWMCHC), control the

output of the three-phase timing unit.

PWM Switching Frequency, PWMTM Register

The PWM switching frequency is controlled by the PWM pe-

riod register, PWMTM. The fundamental timing unit of

the PWM controller is tCK = 1/fCLKOUT where fCLKOUT is the

CLKOUT frequency (DSP instruction rate). Therefore, for a

25 MHz CLKOUT, the fundamental time increment is 40 ns.

The value written to the PWMTM register is effectively the

number of tCK clock increments in half a PWM period. The

required PWMTM value as a function of the desired PWM

switching frequency (fPWM) and is given by:

PWMTM

f CLKOUT

× f

PWM

f CLKIN

f PWM

Therefore, the PWM switching period, TS, can be written as:

TS = 2

× tCK × PWMTM

For example, for a 25 MHz CLKOUT and a desired PWM

switching frequency of 10 kHz (TS = 100

µs), the correct value

to load into the PWMTM register is:

PWMTM

×106

×10 ×103

=1250

The largest value that can be written to the 16-bit PWMTM

PWM switching frequency of:

f PWM, MIN

×106

×65,535

=190.74 Hz

for a CLKOUT frequency of 25 MHz.

PWM Switching Dead Time, PWMDT Register

The second important parameter that must be set up in the

initial configuration of the PWM block is the switching dead

time. This is a short delay time introduced between turning off

one PWM signal (say, AH) and turning on the complementary

signal, AL. This short time delay is introduced to permit the

power switch being turned off (in this case, AH) to completely

recover its blocking capability before the complementary switch

is turned on. This time delay prevents a potentially destructive

short-circuit condition from developing across the dc link

capacitor of a typical voltage source inverter.

The dead time is controlled by the 10-bit, read/write PWMDT

dead time inserted into all three pairs of PWM output signals.

The dead time, TD, is related to the value in the PWMDT regis-

ter by:

T D

= PWMDT × 2 × t

× PWMDT

f CLKOUT

Therefore, a PWMDT value of 0x00A (= 10), introduces an

800 ns delay between the turn-off on any PWM signal (say, AH)

and the turn-on of its complementary signal (AL). The amount

of the dead time can therefore be programmed in increments of

2tCK (or 80 ns for a 25 MHz CLKOUT). The PWMDT register

is a 10-bit register so that its maximum value is 0x3FF (= 1023),

corresponding to a maximum programmed dead time of:

T D, MAX

=1023 × 2 × t

=1023 × 2 × 40 ×10–9 = 81.84 µs

for a CLKOUT rate of 25 MHz. Obviously, the dead time can

be programmed to be zero by writing 0 to the PWMDT register.

PWM Operating Mode, MODECTRL and SYSSTAT Registers

The PWM controller of the ADMC300 can operate in two

distinct modes; single update mode and double update mode.

The operating mode of the PWM controller is determined by

the state of Bit 6 of the MODECTRL register. If this bit is

cleared the PWM operates in the single update mode. Setting

Bit 6 places the PWM in the double update mode. By default,

following either a peripheral reset or power-on, Bit 6 of the

MODECTRL register is cleared so that the default operating

mode is single update mode.

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